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NLAS4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
http://onsemi.com
The NLAS4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS
technology for lower R
DS(on)
resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to
±3.0
V to pass a 6.0 V
PP
signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings.
Features
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
NLAS4051G
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
1
NLAS
4051
ALYWG
G
•
Improved R
DS(on)
Specifications
•
Pin for Pin Replacement for MAX4051 and MAX4051A
One Half the Resistance Operating at 5.0 V
•
Single or Dual Supply Operation
♦
Single 2.5−5.0 V Operation, or Dual
±3.0
V Operation
♦
With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V
Logic, No Translators Needed
♦
Address and Inhibit Logic are Over−Voltage Tolerant and May
Be Driven Up +6.0 V Regardless of V
CC
•
Improved Linearity Over Standard HC4051 Devices
♦
1
16
QSOP−16
QS SUFFIX
CASE 492
1
A
WL, L
Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
S4051
ALYW
1
•
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
•
Pb−Free Packages are Available*
V
CC
16
NO
2
15
NO
4
14
NO
0
13
NO
6
ADD
C
ADD
B
ADD
A
12
11
10
9
ORDERING INFORMATION
Device
NLAS4051DR2
NLAS4051DR2G
NLAS4051DTR2
Package
SOIC−16
SOIC−16
(Pb−Free)
Shipping
†
2500/Tape & Reel
2500/Tape & Reel
TSSOP−16 2500/Tape & Reel
1
NO
1
2
3
4
NO
7
5
NO
5
6
7
8
GND
NO
3
COM
Inhibit V
EE
NLAS4051DTR2G TSSOP−16 2500/Tape & Reel
(Pb−Free)
NLAS4051QSR
QSOP−16
2500/Tape & Reel
Figure 1. Pin Connection
(Top View)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
May, 2006 − Rev. 3
Publication Order Number:
NLAS4051/D
NLAS4051
TRUTH TABLE
Address
Inhibit
1
0
0
0
0
0
0
0
0
C
X
don’t care
0
0
0
0
1
1
1
1
B
X
don’t care
0
0
1
1
0
0
1
1
A
X
don’t care
0
1
0
1
0
1
0
1
ON SWITCHES*
NO
2
All switches open
COM−NO
0
COM−NO
1
COM−NO
2
COM−NO
3
COM−NO
4
COM−NO
5
COM−NO
6
COM−NO
7
ADD
C
ADD
B
ADD
A
LOGIC
COM
NO
3
NO
4
NO
5
NO
6
NO
7
Inhibit
NO
0
NO
1
*NO and COM pins are identical and interchangeable. Either may be considered
an input or output; signals pass equally well in either direction.
Figure 2. Logic Diagram
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ Î
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Parameter
Symbol
V
EE
Value
Unit
V
V
V
V
Negative DC Supply Voltage
(Referenced to GND)
−7.0 to
)0.5
−0.5 to
)7.0
−0.5 to
)7.0
Positive DC Supply Voltage (Note 1)
Analog Input Voltage
Digital Input Voltage
(Referenced to GND)
(Referenced to V
EE
)
V
CC
V
IS
V
EE
−0.5 to V
CC
)0.5
−0.5 to 7.0
$50
(Referenced to GND)
V
IN
I
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
_C
_C
_C
−65 to
)150
260
T
STG
T
L
T
J
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
)150
143
164
164
500
450
450
SOIC
TSSOP
QSOP
SOIC
TSSOP
QSOP
q
JA
°C/W
Power Dissipation in Still Air,
P
D
mW
Moisture Sensitivity
MSL
F
R
Level 1
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
u2000
u200
u1000
$300
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
V
ESD
V
Latchup Performance
Above V
CC
and Below GND at 125°C (Note 5)
I
LATCHUP
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V
CC
$|V
EE
|
≤
7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
http://onsemi.com
2
NLAS4051
RECOMMENDED OPERATING CONDITIONS
ÎÎ ÎÎ
Î
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Parameter
Symbol
V
EE
Min
Max
Unit
V
V
V
V
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
(Referenced to GND)
−5.5
2.5
2.5
GND
5.5
6.6
(Referenced to GND)
(Referenced to V
EE
)
V
CC
V
IS
V
EE
0
V
CC
5.5
(Note 6) (Referenced to GND)
V
IN
T
A
Operating Temperature Range, All Package Types
−55
0
0
125
100
20
_C
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 3.0 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
t
r
, t
f
ns/V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DC CHARACTERISTICS − Digital Section
(Voltages Referenced to GND)
V
CC
V
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
0 V to 6.0 V
6.0
Guaranteed Limit
−55
to 25°C
1.75
2.1
3.15
3.85
.45
0.9
1.35
1.65
$0.1
4.0
v85°C
1.75
2.1
3.15
3.85
.45
0.9
1.35
1.65
$1.0
40
v125°C
1.75
2.1
3.15
3.85
.45
0.9
1.35
1.65
$1.0
80
Unit
V
Parameter
Minimum High−Level Input Voltage,
Address and Inhibit Inputs
Condition
Symbol
V
IH
Maximum Low−Level Input Voltage,
Address and Inhibit Inputs
V
IL
V
Maximum Input Leakage Current,
Address or Inhibit Inputs
Maximum Quiescent Supply Current
(per Package)
V
IN
= 6.0 or GND
Address, Inhibit and
V
IS
= V
CC
or GND
I
IN
I
CC
mA
mA
DC ELECTRICAL CHARACTERISTICS − Analog Section
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î
Î Î Î
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎ
ÎÎ Î Î
Î Î Î
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎ Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î
Symbol
Parameter
Test Conditions
V
CC
V
3.0
4.5
3.0
3.0
4.5
3.0
V
EE
V
Guaranteed Limit
v85_C
108
46
33
20
18
15
4
2
−55 to 25°C
86
37
26
15
13
10
4
2
v125_C
120
55
37
20
18
15
5
3
Unit
W
Maximum “ON” Resistance
(Note 7)
V
IN
= V
IL
or V
IH
V
IS
= (V
EE
to V
CC
)
|I
S
| = 10 mA
(Figures 4 thru 9)
R
ON
0
0
−3.0
0
0
−3.0
3.0
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
IN
= V
IL
or V
IH,
V
IS
= 2.0 V
V
IS
=
½
(V
CC
− V
EE
), V
IS
= 3.0 V
|I
S
| = 10 mA, V
IS
= 2.0 V
DR
ON
W
ON Resistance Flatness
Maximum Off−Channel
Leakage Current
|I
S
| = 10 mA V
COM
= 1, 2, 3.5 V
V
COM
= 2, 0, 2 V
Rflat(ON)
I
NC(OFF)
I
NO(OFF)
4.5
3.0
W
Switch Off
V
IN
= V
IL
or V
IH
V
IO
= V
CC
−1.0 V or V
EE
+1.0 V
(Figure 17)
Switch On
V
IO
= V
CC
−1.0 V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
Maximum On−Channel
Leakage Current,
Channel− to−Channel
I
COM(ON)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
7. At supply voltage (V
CC
) approaching 2.5 V the analog switch on−resistance becomes extremely non−linear. Therefore, for low voltage
operation it is recommended that these devices only be used to control digital signals.
http://onsemi.com
3
NLAS4051
AC CHARACTERISTICS
(Input t
r
= t
f
= 3 ns)
ÎÎ Î Î Î Î
Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎ Î
ÎÎÎÎÎ ÎÎ Î
Î Î ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î ÎÎ Î
Î
Guaranteed Limit
Parameter
Test Conditions
Symbol
t
BBM
V
CC
V
3.0
4.5
3.0
V
EE
V
−55 to 25_C
Min
1.0
1.0
1.0
Typ*
6.5
5.0
3.5
v85_C
−
−
−
v125_C
−
−
−
Unit
ns
Minimum Break−Before−
Make Time
V
IN
= V
IL
or V
IH
V
IS
= V
CC
R
L
= 300
W,
C
L
= 35 pF
(Figure 19)
0.0
0.0
−3.0
*Typical Characteristics are at 25_C.
AC CHARACTERISTICS
(C
L
= 35 pF, Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
V
EE
V
0
0
0
−3.0
0
0
0
−3.0
0
0
0
−3.0
−55 to 25°C
Min
Typ
22
20
16
16
22
18
16
16
22
18
16
16
Max
40
28
23
23
40
28
23
23
40
28
23
23
v85°C
Min
Max
45
30
25
25
45
30
25
25
45
30
25
25
v125°C
Min
Max
50
35
30
28
50
35
30
28
50
35
30
28
Unit
ns
Parameter
Transition Time
(Address Selection Time)
(Figure 18)
Turn−on Time
(Figures 14, 15, 20, and 21)
Inhibit to N
O
or N
C
Turn−off Time
(Figures 14, 15, 20, and 21)
Inhibit to N
O
or N
C
Symbol
t
TRANS
t
ON
ns
t
OFF
ns
Typical @ 25°C, V
CC
= 5.0 V
Maximum Input Capacitance, Select Inputs
Analog I/O
Common I/O
Feedthrough
C
IN
C
NO
or C
NC
C
COM
C
(ON)
8
10
10
1.0
pF
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
Symbol
BW
V
CC
V
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
5.0
3.0
V
EE
V
0.0
0.0
0.0
−3.0
0.0
0.0
0.0
−3.0
0.0
0.0
0.0
−3.0
0.0
−3.0
Typ
25°C
80
90
95
95
−93
−93
−93
−93
−2
−2
−2
−2
9.0
12
Unit
MHz
Parameter
Maximum On−Channel Bandwidth or
Minimum Frequency Response
Condition
V
IS
=
½
(V
CC
− V
EE
)
Source Amplitude = 0 dBm
(Figures 10 and 22)
f =100 kHz; V
IS
=
½
(V
CC
− V
EE
)
Source = 0 dBm
(Figures 12 and 22)
V
IS
=
½
(V
CC
− V
EE
)
Source = 0 dBm
(Figures 10 and 22)
V
IN
= V
CC
to V
EE,
f
IS
= 1 kHz, t
r
= t
f
= 3 ns
R
IS
= 0
W,
C
L
= 1000 pF, Q = C
L
*
DV
OUT
(Figures 16 and 23)
f
IS
= 1 MHz, R
L
= 10 KW, C
L
= 50 pF,
V
IS
= 5.0 V
PP
sine wave
V
IS
= 6.0 V
PP
sine wave
(Figure 13)
Off−Channel Feedthrough Isolation
V
ISO
dB
Maximum Feedthrough On Loss
V
ONL
dB
Charge Injection
Q
pC
Total Harmonic Distortion THD + Noise
THD
6.0
3.0
0.0
−3.0
0.10
0.05
%
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