BX80560KF3000H datasheet, PDF - EEWORLD Datasheet

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BX80560KF3000H: DescriptionMicroprocessor, 64-Bit, 3000MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，108 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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BX80560KF3000H Overview

Microprocessor, 64-Bit, 3000MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604

BX80560KF3000H Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
Parts packaging code	PGA
package instruction	SPGA,
Contacts	604
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	40
bit size	64
boundary scan	YES
maximum clock frequency	667 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P604
length	53.34 mm
low power mode	YES
Number of terminals	604
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified
Maximum seat height	4.841 mm
speed	3000 MHz
Maximum supply voltage	1.41 V
Minimum supply voltage	1.26 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	53.34 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Dual-Core Intel

Xeon

Processor 7000 Series

Datasheet

Revision 2.1

September 2006

Document Number: 309626-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Dual-Core Intel

Xeon

Processor 7000 Series may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for Inte

64 architecture. Processors will not operate (including 32-bit operation) without an Intel

64 architecture-enabled BIOS.

Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Intel, Intel Xeon, Intel NetBurst and Intel SpeedStep are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United

States and other countries.

*Other names and brands may be claimed as the property of others.

Dual-Core Intel

Xeon

Processor 7000 Series Datasheet

Contents

Introduction....................................................................................................................... 11

1.1

Terminology......................................................................................................... 12

1.2

Reference Documents......................................................................................... 14

1.3

State of Data ....................................................................................................... 14

Electrical Specifications.................................................................................................... 15

2.1

Front Side Bus and GTLREF .............................................................................. 15

2.1.1 Front Side Bus Clock and Processor Clocking....................................... 15

2.1.2 Front Side Bus Clock Select (BSEL[1:0]) ............................................... 16

2.1.3 Phase Lock Loop (PLL) Power and Filter............................................... 17

2.2

Voltage Identification (VID).................................................................................. 17

2.3

Reserved, Unused, and TESTHI Pins.................................................................20

2.4

Mixing Processors ............................................................................................... 20

2.5

Front Side Bus Signal Groups............................................................................. 21

2.6

GTL+ Asynchronous Signals and AGTL + Asynchronous Signals...................... 22

2.7

Test Access Port (TAP) Connection.................................................................... 23

2.8

Absolute Maximum and Minimum Ratings .......................................................... 23

2.9

Processor DC Specifications............................................................................... 24

2.9.1 Flexible Motherboard (FMB) Guidelines................................................. 24

2.9.2 Vcc Overshoot Specification .................................................................. 28

Mechanical Specifications ................................................................................................ 33

3.1

Package Mechanical Drawing ............................................................................. 33

3.2

Processor Component Keepout Zones ............................................................... 36

3.3

Package Loading Specifications ......................................................................... 36

3.4

Package Handling Guidelines ............................................................................. 37

3.5

Package Insertion Specifications ........................................................................ 37

3.6

Processor Mass Specifications ........................................................................... 37

3.7

Processor Materials............................................................................................. 37

3.8

Processor Markings............................................................................................. 38

3.9

Processor Pin-Out Coordinates........................................................................... 39

Pin Listing......................................................................................................................... 41

4.1

Dual-Core Intel Xeon Processor 7000 Series Pin Assignments.......................... 41

4.1.1 Pin Listing by Pin Name ......................................................................... 41

4.1.2 Pin Listing by Pin Number ...................................................................... 50

Signal Definitions.............................................................................................................. 59

5.1

Signal Definitions................................................................................................. 59

Thermal Specifications ..................................................................................................... 67

6.1

Package Thermal Specifications ......................................................................... 67

6.1.1 Thermal Specifications ........................................................................... 67

6.1.2 Thermal Metrology ................................................................................. 70

6.2

Processor Thermal Features............................................................................... 70

6.2.1 Thermal Monitor ..................................................................................... 70

Dual-Core Intel

Xeon

Processor 7000 Series Datasheet

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

On-Demand Mode.................................................................................. 71

PROCHOT# Signal Pin .......................................................................... 71

FORCEPR# Signal Pin .......................................................................... 72

THERMTRIP# Signal Pin ....................................................................... 72

Tcontrol and Fan Speed Reduction ....................................................... 72

Thermal Diode........................................................................................ 72

Features ........................................................................................................................... 73

7.1

Power-On Configuration Options ........................................................................ 73

7.2

Clock Control and Low Power States.................................................................. 73

7.2.1 Normal State .......................................................................................... 73

7.2.2 HALT Power Down State ....................................................................... 74

7.2.3 Stop-Grant State .................................................................................... 74

7.2.4 HALT/Grant Snoop State ....................................................................... 75

7.2.5 Enhanced HALT Powerdown State........................................................ 75

7.3

Enhanced Intel SpeedStep

Technology............................................................ 76

7.4

System Management Bus (SMBus) Interface ..................................................... 76

7.4.1 Processor Information ROM (PIROM).................................................... 77

7.4.2 Scratch EEPROM .................................................................................. 80

7.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ........... 80

7.4.4 SMBus Thermal Sensor ......................................................................... 81

7.4.5 Thermal Sensor Supported SMBus Transactions .................................. 81

7.4.6 SMBus Thermal Sensor Registers ......................................................... 84

7.4.7 SMBus Thermal Sensor Alert Interrupt .................................................. 87

7.4.8 SMBus Device Addressing..................................................................... 88

7.4.9 Managing Data in the PIROM ................................................................ 89

Boxed Processor Specifications....................................................................................... 97

8.1

Introduction ......................................................................................................... 97

8.2

Mechanical Specifications ................................................................................... 98

8.2.1 Boxed Processor Heatsink Dimensions ................................................. 98

8.2.2 Boxed Processor Heatsink Weight....................................................... 104

8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports......... 104

8.3

Thermal Specifications...................................................................................... 105

8.3.1 Boxed Processor Cooling Requirements ............................................. 105

8.3.2 Boxed Processor Contents .................................................................. 105

Debug Tools Specifications............................................................................................ 107

9.1

Logic Analyzer Interface (LAI) ........................................................................... 107

9.1.1 Mechanical Considerations .................................................................. 107

9.1.2 Electrical Considerations...................................................................... 107

Dual-Core Intel

Xeon

Processor 7000 Series Datasheet

Figures

2-1

2-2

2-3

2-4

2-5

3-1

3-2

3-3

3-4

3-5

3-6

3-7

6-1

6-2

7-1

7-2

8-1

8-2

8-3

8-4

8-5

8-6

8-7

On-Die Front Side Bus Termination .................................................................... 15

Phase Lock Loop (PLL) Filter Requirements ...................................................... 17

Dual-Core Intel

Xeon

Processor 7000 SeriesLoad

Current vs. Time.................................................................................................. 26

VCC Static and Transient Tolerance................................................................... 28

Overshoot Example Waveform.................................................................... 29

Processor Package Assembly Sketch.................................................................33

Processor Package Drawing (Sheet 1 of 2) ........................................................ 34

Processor Package Drawing (Sheet 2 of 2) ........................................................ 35

Processor Topside Markings............................................................................... 38

Processor Bottom-Side Markings........................................................................ 38

Processor Pin-Out Coordinates, Top View.......................................................... 39

Processor Pin-Out Coordinates, Bottom View ....................................................40

Dual-Core Intel

Xeon

Processor 7000 Series Thermal Profile A .................... 69

Case Temperature (TCASE) Measurement Location ......................................... 70

Stop Clock State Machine ................................................................................... 74

Logical Schematic of SMBus Circuitry ................................................................ 77

Passive Dual-Core Intel

Xeon

Processor 7000 Series

Thermal Solution (3U and Larger)....................................................................... 97

Top Side Board Keepout Zones (Part 1) ............................................................. 99

Top Side Board Keepout Zones (Part 2) ...........................................................100

Bottom Side Board Keepout Zones...................................................................101

Board Mounting-Hole Keepout Zones ...............................................................102

Thermal Solution Volumetric .............................................................................103

Recommended Processor Layout and Pitch .....................................................104

Tables

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-14

2-15

Features of the Dual-Core Intel

Xeon

Processor 7000 Series ........................ 12

Core Frequency to Front Side Bus Multiplier Configuration ................................ 16

BSEL[1:0] Frequency Table for BCLK[1:0].......................................................... 16

Voltage Identification (VID) Definition.................................................................. 19

Front Side Bus Pin Groups.................................................................................. 21

Signal Description Table ..................................................................................... 22

Signal Reference Voltages.................................................................................. 22

Processor Absolute Maximum Ratings ............................................................... 23

Voltage and Current Specifications ..................................................................... 24

VCC Static and Transient Tolerance................................................................... 27

Overshoot Specifications ............................................................................. 28

Front Side Bus Differential BCLK Specifications................................................. 29

BSEL[1:0], VID[5:0], and DC Specifications........................................................ 30

VIDPWRGD DC Specifications ........................................................................... 30

AGTL+ Signal Group DC Specifications ............................................................. 30

PWRGOOD Input and TAP Signal Group DC Specifications.............................. 30

Dual-Core Intel

Xeon

Processor 7000 Series Datasheet

BX80560KF3000H Related Products

	BX80560KF3000H	BX80560KF2660F	BX80560KF3000H/SL8UC	NE80560KG0804MH	NE80560KG0804MH/SL8UD	NE80560KF0804MH	NE80560KF0804MH/SL8UC	NE80560KG0722MH/SL8UB	NE80560KF0672MH	NE80560KG0722MH
Description	Microprocessor, 64-Bit, 3000MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604	Microprocessor, 64-Bit, 2660MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604	RISC Microprocessor, 64-Bit, 3000MHz, CMOS, PPGA604	Microprocessor, 64-Bit, 3000MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604	RISC Microprocessor, 64-Bit, 3000MHz, CMOS, PPGA604	Microprocessor, 64-Bit, 3000MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604	RISC Microprocessor, 64-Bit, 3000MHz, CMOS, PPGA604	RISC Microprocessor, 64-Bit, 2800MHz, CMOS, PPGA604	Microprocessor, 64-Bit, 2660MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604	Microprocessor, 64-Bit, 2800MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604
package instruction	SPGA,	SPGA,	SPGA, PGA604,25X31,50	SPGA,	SPGA, PGA604,25X31,50	SPGA,	SPGA, PGA604,25X31,50	SPGA, PGA604,25X31,50	SPGA,	SPGA,
Reach Compliance Code	compliant	compliant	unknown	compliant	unknown	compliant	unknown	unknown	compliant	compli
bit size	64	64	64	64	64	64	64	64	64	64
JESD-30 code	S-CPGA-P604	S-CPGA-P604	R-PPGA-P604	S-CPGA-P604	R-PPGA-P604	S-CPGA-P604	R-PPGA-P604	R-PPGA-P604	S-CPGA-P604	S-CPGA-P604
Number of terminals	604	604	604	604	604	604	604	604	604	604
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA
Package shape	SQUARE	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
speed	3000 MHz	2660 MHz	3000 MHz	3000 MHz	3000 MHz	3000 MHz	3000 MHz	2800 MHz	2660 MHz	2800 MHz
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR, RISC	MICROPROCESSOR	MICROPROCESSOR, RISC	MICROPROCESSOR	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR	MICROPROCESSOR
Is it Rohs certified?	conform to	conform to	-	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Intel	Intel	-	Intel	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	PGA	PGA	-	PGA	-	PGA	-	-	PGA	PGA
Contacts	604	604	-	604	-	604	-	-	604	604
ECCN code	3A001.A.3	3A001.A.3	-	3A001.A.3	-	3A001.A.3	-	-	3A001.A.3	3A991.A.1
Address bus width	40	40	-	40	-	40	-	-	40	40
boundary scan	YES	YES	-	YES	-	YES	-	-	YES	YES
maximum clock frequency	667 MHz	667 MHz	-	800 MHz	-	667 MHz	-	-	667 MHz	800 MHz
External data bus width	64	64	-	64	-	64	-	-	64	64
Format	FLOATING POINT	FLOATING POINT	-	FLOATING POINT	-	FLOATING POINT	-	-	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	-	YES	-	YES	-	-	YES	YES
length	53.34 mm	53.34 mm	-	53.34 mm	-	53.34 mm	-	-	53.34 mm	53.34 mm
low power mode	YES	YES	-	YES	-	YES	-	-	YES	YES
Maximum seat height	4.841 mm	4.841 mm	-	4.841 mm	-	4.841 mm	-	-	4.841 mm	4.841 mm
Maximum supply voltage	1.41 V	1.41 V	-	1.41 V	-	1.41 V	-	-	1.41 V	1.41 V
Minimum supply voltage	1.26 V	1.26 V	-	1.26 V	-	1.26 V	-	-	1.26 V	1.26 V
width	53.34 mm	53.34 mm	-	53.34 mm	-	53.34 mm	-	-	53.34 mm	53.34 mm

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