3.3V 48 or 24MHz output and Hi- Z state strapping option
(2,5)
Strap Low = Enter Hi- Z state mode for testing, Strap High = N ormal operation
Select for enabling 100 MHz or 66 MHz CPU clock
(5)
H = 100 MHz, L = 66 MHz
Device enters power down mode when LO W5
When Low, stop CPU clocks in LO W state
When signal LO W, stops all PCI clocks in LO W state except for PCICLK _F output
(5)
O utput 48- 24MHz/TS#
Input
Input
Input
Input
O utput
SEL100/66#
PWR_DWN #
CPU_STO P#
PCI_STO P#
CPUCLK [1- 0] 2.5V CPU clock outputs
3.3V 14.318 MHz reference clock output and power- on spread spectrum
enable strap option
(3,5)
REF0/Spread#
Strap Low = Spread spectrum clocking enable
Strap High = Spread spectrum clocking disable
3.3V 14.318 MHz reference clock output and power- on 48/24 MHz
select strap option4,5
REF1/SEL48#
Pin 14 output = 48 MHz when straped LO W
Pin 14 output = 24 MHz when strapped HIGH
V
DD
V
S S
V
DD2
V
SS2
3.3V Power
3.3V Ground
2.5V Power
2.5V Ground
26
1
O utput
27
1
O utput
8,12,19,28
1,7,15,21
25
22
Notes:
1
Power
Power
1
1
Power
Power
1. V
DD
and V
SS
names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the performance
of the device. In reality, the platform will be configured with the same voltage V
DD
pins tied to a common supply and all V
SS
pins being common.
The V
DD
/V
SS
naming convention above is done to show how the pinout is dominated by the need to isolate all the signals.
2. The output frequency at this pin is dependent on the power on strapping option at pin 27. A 48 MHz output when power-on strapped LOW,
and 24 MHz output when strapped HIGH. This pin also serves as Hi-Z state strapping option during power-on configuration. During power-on,
the PI6C103 will sample the value at this pin. Strapped LOW for Hi-Z state mode and HIGH for normal operation.
3. This is a dual function pin. During power-on, all clock outputs are disabled, and the PI6C103 will sample the spread spectrum enable/disable strapping
option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 MHz reference clock
output. The Power-on latency needs to be less than 3ms after the supply voltage stabilized.
4. This is a dual function pin. During power-on, all clocks are disabled, and PI6C103 will sample the SEL48# strapping option. After the strapped
value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 MHz reference clock output. The power-
on latency needs to be less than 3ms after the supply voltage stabilized.
5. Internally pulled up with resistor min.value of 50kΩ.
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