DATA SHEET
JANUARY 1999
Revision 2.0
LXP730
Multi-Rate DSL Framer
General Description
The LXP730 is a multi-purpose Digital Subscriber Line
(DSL) framer which complements the Level One
SK70725/21 Enhanced MDSL Data Pump (EMDP) to
provide seamless transport of data and voice signals over
one or more DSL datapaths.
Features
The LXP730 provides the basic functions required of a
DSL framer:
• Synchronization of external data streams to the DSL
line
• Multiplexing and demultiplexing of independent data
streams for voice and data
• Loopback of payload data at the DSL interface
• Creation, insertion, and recovery of the MDSL
Overhead (MOH) structure, performance monitoring,
and message transport required in a DSL system with
a capacity of up to 32 kbps
• Supports two input/output data streams simultaneously
• Slave mode: external clock determines the rate at
which data will be transferred to and from the
framer
• Master mode: clock derived from received DSL
clock or external oscillator
• Single part architecture allows one chip to be used
economically in both central and remote locations
• Supports systems with point-to-point architectures
• Alternate Hardware Control mode (HWC) for
operation without an external microprocessor
Applications
The LXP730 in combination with the EMDP chipset is
optimized for use as a framer or I/O interface device for the
following applications:
• Digital Pair Gain Systems
• Ethernet Modems
• T1/E1 Fractional Transport Systems
• Videoconferencing Systems
• Simultaneous Data - Voice Transport Systems
• Wireless Base Station Access Systems
LXP730 Block Diagram
PCM-Bus
Interface
Slip
Buffer
Time Slot
Interchange
(TSI)
MX Elastic
Store
MOH MX
Codec
Interface
Shared
Async
Data Port
Interface
(ADPI)
Registers
Stuff
DX Elastic
Store
MDSL
Interface
MOH DX
Overhead
Serial I/O
(OSIO)
Interface
Recovered Clock All Digital PLL
(ADPLL)
Receive
Framer
Microprocessor
Interface
Clock Generation and Distribution
Refer to www.level1.com for most current information.
)
LXP730 Multi-Rate DSL Framer
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXP730 Pin Assignments
GND
TES T 1
FR M S YN C 4
FR M S YN C 5
FR M S YN C 6
FR M S YN C 7
F R M S YN C 8
M O T EL/H W C
R ES ET
FR M S YN C 9
FR M S YN C 1 0
FR M S YN C 11
FR M S YN C 1 2
G AP _C LK
O SIF
GND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
V CC
C C LK/TC L KO
C D ATO
CD AT I
F R M SY NC 1
FR M S Y NC 2
F RM S YN C 3
M C LK
V CC
GND
T ES T 2
PD I/T1E 1l/Z
1
PF R M /FR M IN /Z
0
P C LK /TC LK I
P D O/T1 E1O /Z
2
VC C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-P IN
LQ FP
V CC
R D ATA
Q U ATC L K
TD ATA
OSOF
B IT C LK
IN T
A LE/H T U _S E L
( R D )/H W C
R /W ( W R )/H W C
C S/H W C
D ATA7
D ATA6
D ATA5
D ATA4
V CC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 1: LXP730 Pin Descriptions
Pin
1, 9,
16, 33,
48
10, 17,
32, 49,
64
28
29
30
31
34
Symbol
VCC
Type
1
Description
Power Supply.
_
_
DI/O,
DO
DI/O,
DO
DI/O,
DO
GND
Ground.
DATA0/
CRC_ERROR
DATA1/FEBE
DATA2/
LINK_ACTIVE
DATA3/RUN-
STOP
DATA4/
FRMSYNC15
DATA0.
MPC mode/CRC_ERROR. flag HWC mode, indicates an error was
detected in the previous frame.
DATA1.
MPC mode/FEBE. flag HWC mode, indicates the other side of the
DSL link encountered a CRC error.
DATA2.
MPC mode/LINK_ACTIVE. HWC mode, indicates that the DSL
link is active and ready to transport data.
DI/O, DI
DATA3.
MPC mode/RUN-STOP. HWC mode, set to low to activate the DSL
link, edge triggered input.
DI/O,
DO
DATA4.
MPC mode /FRMSYNC15. HWC mode, Frame Sync Pulse, channel
15.
1. AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; NC = No Clamp. Pad will not clamp input in the absence of
power; PU = Input contains pull-up; PD = Input contains pull-down; I/O = Input/Output; OD = Open Drain Output; TO = Tri-State Output.
2
GND
OSDO
OSDOCK
O SD I
O S D IC K
ADDR0
AD D R 1
ADDR2
ADDR3
ADDR4
ADDR5
D ATA 0
D ATA1
D ATA 2
D ATA 3
GND
32
)
LXP730 Pin Assignments and Signal Descriptions
Table 1: LXP730 Pin Descriptions
– continued
Pin
35
36
37
22
23
24
25
26
27
57
39
40
38
41
42
56
8
4
3
2
5
6
7
62
61
60
Symbol
DATA5/
FRMSYNC16
DATA6/
FRMSYNC17
DATA7/
FRMSYNC18
ADDR0/
FRMSYNC13
ADDR1/N1
ADDR2/N2
ADDR3/N3
ADDR4/N4
ADDR5/
FRMSYNC14
MOTEL/HWC
R/W(WR)/HWC
select
(RD)/HWC
select
CS /HWC select
ALE/HTU_SEL
INT
RESET
MCLK
CDATI
CDATO
CCLK/TCLKO
FRMSYNC1/
FRMOUT
FRMSYNC2
FRMSYNC3
FRMSYNC4
FRMSYNC5
FRMSYNC6
Type
1
DI/O,
DO
DI/O,
DO
DI/O,
DO
DI, DO
DI
DI
DI
DI
DI, DO
DI
DI
DI
DI
DI
DO
DI
DI
DI
TO
TO
DO
DO
DO
DO
DO
DO
Description
DATA5.
MPC mode /FRMSYNC16. HWC mode. Frame Sync Pulse, channel
16.
DATA6.
MPC mode /FRMSYNC17. HWC mode. Frame Sync Pulse, channel
17.
DATA7.
MPC mode /FRMSYNC18. HWC mode. Frame Sync Pulse, channel
17.
ADDR0.
MPC mode/FRMSYNC13. HWC mode. Frame Sync Pulse, channel
13, output.
ADDR1.
MPC mode/N1. DSL rate select, HWC mode.
ADDR2.
MPC mode/N2. DSL rate select, HWC mode.
ADDR3.
MPC mode/N3. DSL rate select, HWC mode.
ADDR4.
MPC mode/N4. DSL rate select, HWC mode.
ADDR5.
MPC mode/FRMSYNC14. Frame Sync Pulse, channel 14, output,
HWC mode.
MOTEL/HWC.
Set high for Motorola mode, set low for Intel mode, Micro
Processor Control (MPC) mode, input
/HWC.
pull high for HWC mode, input.
R/W(WR).
R/W for Motorola interface, WR for Intel interface /HWC select,
set low for HWC mode.
(RD).
Unused for Motorola interface, RD for Intel interface /HWC select, set
low for HWC mode.
CS.
Chip select, HWC select, set low for HWC mode.
ALE.
Address latch enable for Intel interface, MPC mode, input
/HTU_SEL.
HTUC/HTUR select, High for HTUC, Low for HTUR, HWC mode, input.
INT.
Interrupt output. Programmed by setting bits in the INT_EN register.
RESET.
Active low input. All registers revert to their default values.
MCLK.
Master Clock.
CDATI.
Codec Data In.
CDATO.
Codec Data Out, Tri-state.
CCLK.
Codec Clock, Nominal 2.048 MHz, tri-state. /TCLKO. Transport
Clock for T1/E1: 1.544 MHz or 2.048 MHz clock derived from line rate.
FRMSYNC1.
Frame Sync Pulse, channel 1, output. /FRMOUT. Frame Out,
for T1/E1 application, output.
FRMSYNC2.
Frame Sync Pulse, channel 2, output.
FRMSYNC3.
Frame Sync Pulse, channel 3, output.
FRMSYNC4.
Frame Sync Pulse, channel 4, output.
FRMSYNC5.
Frame Sync Pulse, channel 5, output.
FRMSYNC6.
Frame Sync Pulse, channel 6, output.
1. AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; NC = No Clamp. Pad will not clamp input in the absence of
power; PU = Input contains pull-up; PD = Input contains pull-down; I/O = Input/Output; OD = Open Drain Output; TO = Tri-State Output.
)
3
LXP730 Multi-Rate DSL Framer
Table 1: LXP730 Pin Descriptions
– continued
Pin
59
58
55
54
53
52
Symbol
FRMSYNC7/
SDOCK
FRMSYNC8/
SDO
FRMSYNC9
SDICK
FRMSYNC10/
SDI
FRMSYNC11
FRMSYNC12/
PDOE
GAP_CLK
TEST1
TEST2
OSDICK
OSDI
OSDOCK
OSDO
OSOF
OSIF
TDATA
RDATA
QUATCLK
BITCLK
PFRM / FRMIN
/ Z
0
Type
1
DO
DO
DO
DO, DI
DO
DO
Description
FRMSYNC7.
Frame Sync Pulse, channel 7, output.
/SDOCK.
Serial Data Out
Clock, ADPI serial mode, output.
FRMSYNC8.
Frame Sync Pulse, channel 8, output.
/SDO.
Serial Data Out,
ADPI serial mode, output.
FRMSYNC9.
Frame Sync Pulse, channel 9, output.
/SDICK.
Serial Data In
Clock, ADPI serial mode, output.
FRMSYNC10.
Frame Sync Pulse, channel 10, output. /SDI. Serial Data In,
ADPI serial mode, input.
FRMSYNC11.
Frame Sync Pulse, channel 11, output.
FRMSYNC12.
Frame Sync Pulse, channel 12, output. /PDOE. PCM Data
Output Enable, control for external PCM interface buffer, output. Enabled by
bit-3 of Register 23h.
GAP_CLK.
Gapped Clock, N x 64 kHz recovered from DSL for optional
external ADPLL, output. Output is high when option not selected.
TEST1.
Factory Test Pin 1, input; should be tied to GND.
TEST2.
Factory Test Pin 2, input; should be tied to VCC.
OSDCKI.
Overhead Serial Data In Clock, output.
OSDI.
Overhead Serial Data In, input.
OSDOCK.
Overhead Serial Data Out Clock, output.
OSDO.
Overhead Serial Data Out, output.
OSOF.
Overhead Serial Output Flag, output. Indicates the first bit of OSIO
output frame.
OSIF.
Overhead Serial Input Flag, output. Indicates the first bit of OSIO input
frame.
TDATA.
Transmit Data, output. Connect to SK70725.
RDATA.
Receive Data, input. Connect to SK70725.
QUATCLK.
Quaternary alignment Clock, input. Connect to SK70725.
BITCLK.
Bit Clock, input. Connect to SK70725.
PFRM.
PCM frame pulse: input for PCM slave, output for PCM master.
Alignment signal for the first time slot for both PDI and PDO. /FRMIN. Frame
In, for T1/E1 application, input. /Z
o
. Bit zero of the 3-bit word used to specify
the number of Z bits in the Hardware mode, input.
PDI.
PCM Data In, input.
/T1E1I.
T1 or E1 Input data, input. /Z
1
.
Bit one of the
3-bit word used to specify the number of Z bits in the Hardware mode, input.
PDO.
PCM Data Out, tri-stateable output.
/T1E1O.
T1 or E1 Output data, tri-
stateable output. /Z
2
.
Bit two of the 3-bit word used to specify the number of Z
bits in the Hardware mode, input.
PCLK.
PCM clock: input for PCM slave, output for PCM master.
/TCLKI.
Transport Clock In, for T1/E1 application, 1.544MHZ - T1, 2.048MHz - E1, input.
51
63
11
21
20
19
18
44
50
45
47
46
43
13
DO
DI
DI
DO
PU
DO
DO
DO
DO
DO
DI
DI
DI
DI,DO,
DI
12
15
PDI / T1E1I / Z
1
PDO / T1E1O /
Z
2
PCLK/TCLKI
PU,DI,
DI
TO,TO,
DI
DI/O
14
1. AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; NC = No Clamp. Pad will not clamp input in the absence of
power; PU = Input contains pull-up; PD = Input contains pull-down; I/O = Input/Output; OD = Open Drain Output; TO = Tri-State Output.
4
)
LXP730 Functional Description
FUNCTIONAL DESCRIPTION
LXP730 Nx64 Framer
The LXP730 is designed to multiplex/demultiplex two
payload sources to/from a DSL stream, and add/recover
overhead data for link control. Several popular interfaces
are provided to support a variety of applications.
The two major categories of payload supported are
synchronous (i.e. voice-frequency data - PCM) and
asynchronous (i.e. digital data - Packet/Cell). The LXP730
supports
Nx64
kbps channels in the DSL with
N
= 4 to 18.
The LXP730 consists of the following functional blocks as
shown on page 1:
• Time Slot Interchange (TSI)
• PCM-Bus Interface
• Codec Interface
• T1/E1 Interface
• Asynchronous Data Port Interface (ADPI)
• Microprocessor Interface
• Overhead Serial I/O (OSIO) Interface
• SK70725/SK70721 (MDSL) Interface
• All Digital PLL (ADPLL)
• Clock Generation and Distribution
The terms Local and Remote are used in this document to
designate the two ends of a DSL link. The Local is usually
the master in that it initiates the link startup and can control
the actions and configuration of the Remote. There are
several equivalent nomenclatures in the Telecom industry.
Some of these are, respectively: CO and CPE, or HTU-C and
HTU-R, or LTU and NTU.
The following is a description of the LXP730 functional
blocks.
In the MX direction (from the TSI to the MDSL Interface),
the TSI multiplexes the payload sources into the MX elastic
store (MX ES). The payload and overhead are multiplexed
into the DSL stream for loop transport.
In the DX direction (from the MSDL Interface to the TSI),
the TSI reads from the DX elastic store (DX ES) and
demultiplexes the loop data into its payload data sources.
Synchronous payload sources are typically 8-bit serial time
slots, cascaded together with each source repeating every
125 µsec (i.e. 8 kHz). A framing pulse, separate from the
data signal, signifies the start of a frame. A 2.048 Mbps data
stream has 32 time slot sources, while a 1.544 Mbps data
stream has 24 time slot sources plus one extra bit for
framing.
When the PCM or codec interfaces are running, the framing
pulses are used by the TSI to initialize operation to the MX
ES. The MX ES and DX ES have triple buffering schemes
that prevent the loss of data. The PCM/codec interfaces
typically produce high speed data bursts while the MDSL
interface runs at a slower though irregular rate.
Asynchronous data is typically a sequence of bytes which
have no explicit timing relationship between them.
Asynchronous Data Port Interface (ADPI) bytes may be
inserted into payload slots that are not carrying PCM data.
ADPI bytes are inserted into the DSL stream in the order
they are received from the interface.
Channel blocking on a MDSL channel is achieved by
setting the CH_CFG bits in the Nx register to 01. The
transported value for that MDSL channel will be the one
stored in the IDLE register.
The TSI uses the MCLK clock to synchronize to the various
interfaces. The MCLK frequency must be at least three
times the highest interface clock frequency for the TSI to
function properly. There are other considerations to select
the operating frequency of MCLK when using the internal
ADPLL.
Time Slot Interchange (TSI)
The Time Slot Interchange (TSI) is the central module of
the LXP730 Nx64 framer. The TSI maps payload to the
available DSL N-channels for transport across the loop.
The TSI uses register settings to select time slots to map into
the N MDSL channels. The total number of available
payload channels is
N
and is set by the N_MDSL register
(00h), with selected valid values from 4 to 18. Each of the
18 Nx registers (01h -012h) is used to select the payload
source, and if applicable, the PCM time slot assigned to the
register’s corresponding MDSL channel.
)
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