Freescale Semiconductor
Advance Information
Document Number: MC33988
Rev. 4.0, 11/2009
Dual Intelligent High-current
Self-protected Silicon High Side
Switch (8.0mΩ)
The 33988 is a dual self-protected 8.0mΩ silicon switch used to
replace electromechanical relays, fuses, and discrete devices in
power management applications. The 33988 is designed for harsh
environments, and it includes self-recovery features. The device is
suitable for loads with high inrush current, as well as motors and all
types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the
Serial Peripheral Interface (SPI). A dedicated parallel input is
available for alternate and pulse-width modulation (PWM) control of
each output. SPI-programmable fault trip thresholds allow the device
to be adjusted for optimal performance in the application.
The 33988 is packaged in a power-enhanced 12 x 12 nonleaded
PQFN package with exposed tabs.
Features
Dual 8.0mΩ max high side switch with parallel input or SPI control
6.0V to 27V operating voltage with standby currents < 5.0μA
Output current monitoring with two SPI-selectable current ratios
SPI control of over-current limit, over-current fault blanking time,
output-OFF open load detection, output ON/OFF control,
watchdog timeout, slew rates, and fault status reporting
• SPI status reporting of overcurrent, open and shorted loads, over-
temperature, under-voltage and over-voltage shutdown, fail-safe
pin status, and program status
• Enhanced -16V reverse polarity V
PWR
protection
V
DD
V
DD
V
DD
V
PWR
33988
HIGH SIDE SWITCH
BOTTOM VIEW
PNA SUFFIX
98ARL10521D
16-PIN PQFN
•
•
•
•
ORDERING INFORMATION
Device
MC33988CPNA
Temperature
Range (T
A
)
- 40°C to 125°C
Package
16 PQFN
33988
VDD
I/O
I/O
SO
SCLK
FS
WAKE
SI
SCLK
CS
SO
RST
INO
IN1
CSNS
FSI
GND
LOAD
HS0
LOAD
HS1
VPWR
GND
MCU
CS
SI
I/O
I/O
I/O
A/D
Figure 1. 33988 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
V
IC
VDD
I
UP
Internal
Regulator
Over-voltage
Protection
CS
SO
SPI
3.0 MHz
Programmable
Switch Delay
0ms –525ms
Selectable Slew
Rate Gate Drive
SI
SCLK
FS
IN[0:1]
RST
WAKE
Selectable Over-current
High Detection
50A or 37.5A
Selectable Over-
current Low Detection
Blanking Time
0.15ms–155ms
Selectable Over-current
Low Detection
3.75A –12.5A
Open Load
Detection
I
DWN
R
DWN
Over-temperature
Detection
HS0
Logic
HS0
HS1
Programmable
Watchdog
310ms–2500ms
V
IC
I
UP
Selectable
Output Current
Recopy
1/10250 or 1/20500
HS1
FSI
GND
Figure 2. 33988 Simplified Internal Block Diagram
CSNS
33988
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
WAKE
CSNS
SLCK
VDD
15
HS1
RST
FSI
IN0
IN1
12 11 10 9
Figure 3. 33988 Pin Connections (Transparent Top View)
Table 1. Pin Definitions
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on
page 16.
Pin
1
2
3
4
5
6
7
8
9
Pin Name
CSNS
WAKE
RST
IN0
FS
FSI
CS
SCLK
SI
Pin
Function
Output
Input
Input
Input
Output
Input
Input
Input
Input
Formal Name
Output Current Monitoring
Wake
Reset (Active Low)
Direct Input 0
Fault Status (Active Low)
Fail-Safe Input
Chip Select (Active Low)
Serial Clock
Serial Input
Definition
This pin is used to output a current proportional to the designated
HS0-1 output.
This pin is used to input a Logic [1] signal so as to enable the
watchdog timer function.
This input pin is used to initialize the device configuration and fault
registers, as well as place the device in a low-current Sleep mode.
This input pin is used to directly control the output HS0.
This is an open drain configured output requiring an external pull-up
resistor to V
DD
for fault reporting.
The value of the resistance connected between this pin and ground
determines the state of the outputs after a watchdog timeout occurs.
This input pin is connected to a chip select output of a master
microcontroller (MCU).
This input pin is connected to the MCU providing the required bit shift
clock for SPI communication.
This is a command data input pin connected to the SPI Serial Data
Output of the MCU or to the SO pin of the previous device of a daisy
chain of devices.
This is an external voltage input pin used to supply power to the SPI
circuit.
SO
CS
7
FS
SI
8
6
5
4
3
2
1
13
GND
14
VPWR
TRANSPARENT
TOP VIEW
16
HS0
10
VDD
Input
Digital Drain Voltage
(Power)
33988
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. Pin Definitions (continued)
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on
page 16.
Pin
11
12
13
14
15
16
Pin Name
SO
IN1
GND
VPWR
HS1
HS0
Pin
Function
Output
Input
Ground
Input
Output
Output
Formal Name
Serial Output
Direct Input 1
Ground
Positive Power Supply
High Side Output 1
High Side Output 0
Definition
This output pin is connected to the SPI Serial Data Input pin of the
MCU or to the SI pin of the next device of a daisy chain of devices.
This input pin is used to directly control the output HS1.
This pin is the ground for the logic and analog circuitry of the device.
This pin connects to the positive power supply and is the source input
of operational power for the device.
Protected 8.0mΩ high side power output to the load.
Protected 8.0mΩ high side power output to the load.
33988
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
ELECTRICAL RATINGS
Operating Voltage Range
Steady-State
VDD Supply Voltage
Input/Output Voltage
(1)
V
DD
V
IN[0:1]
,
RST
, FSI
CSNS, SI, SCLK,
CS, FS
Symbol
Value
Unit
V
PWR
-16 to 41
-0.3 to 5.5
- 0.3 to 7.0
V
V
V
SO Output Voltage
(1)
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Voltage
Positive
Negative
Output Current
(2)
Output Clamp Energy
(3)
ESD Voltage
(4)
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2, 11, 13, 14)
V
SO
I
CL(WAKE)
I
CL(CSNS)
V
HS
- 0.3 to V
DD
+ 0.3
2.5
10
V
mA
mA
V
41
-15
I
HS[0:1]
E
CL[0:1]
V
ESD1
V
ESD3
±750
±500
30
0.37
A
J
V
± 2000
Notes
1. Exceeding this voltage limit may cause permanent damage to the device.
2. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16mH, R
L
= 0, V
PWR
= 12V, T
J
= 150°C).
4.
ESD1 testing is performed in accordance with the Human Body Model (HBM) (C
ZAP
= 100pF, R
ZAP
= 1500Ω); ESD3 testing is performed
in accordance with the Charge Device Model (CDM), Robotic (Czap=4.0pF).
33988
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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