DATA SHEET
NOVEMBER 1998
Revision 1.3
LXT974A/LXT975A
Fast Ethernet 10/100 Quad Transceivers
General Description
The LXT974A and LXT975A are four-port PHY Fast
Ethernet Transceivers which support IEEE 802.3 physical
layer applications at both 10 Mbps and 100 Mbps. They
provide all of the active circuitry to interface four 802.3
Media Independent Interface (MII) compliant controllers
to 10BASE-T and/or 100BASE-TX media. This data sheet
applies to all LXT974_ and LXT975_ products including
LXT974, LXT975 and any subsequent variants, except as
specifically noted.
All four ports on the LXT974A provide a combination
twisted-pair (TP) or pseudo-ECL (PECL) interface for a
10/100BASE-TX or 100BASE-FX connection.
The LXT975A is pin compatible with the LXT974A except
for the network ports. The LXT975A is optimized for dual-
high stacked RJ45 modular applications and provides a
twisted-pair interface on every port, but the PECL interface
on only two.
The LXT974A/975A provides three separate LED drivers
for each of the four PHY ports and a serial LED interface.
In addition to standard Ethernet, each chip supports full-
duplex operation at 10 Mbps and 100 Mbps. The
LXT974A/975A requires only a single 5V power supply.
The MII may be operated independently with either a 3.3V
or 5V supply.
Features
• Four independent IEEE 802.3-compliant 10BASE-T
or 100BASE-TX ports in a single chip.
• 100BASE-FX fiber-optic capable.
• Standard CSMA/CD or full-duplex operation.
• Supports auto-negotiation and legacy systems without
auto-negotiation capability.
• Baseline wander correction.
• 100BASE-TX line performance over 130 meters.
• Configurable LED drivers and serial LED output.
• Configurable through MII serial port or via external
control pins.
• Available in 160-pin PQFP with heat spreader.
• Commercial temperature range (0-70
o
C ambient).
• Part numbers:
LXT974AHC (new designation)
LXT974QC (original designation)
LXT975AHC (new designation)
LXT975QC (original designation)
Applications
• 10BASE-T, 10/100-TX, or 100BASE-FX Switches
and multi-port NICs.
• LXT975A optimized for dual-high stacked modular
RJ45 applications.
LXT974A/975A Block Diagram
VCCMII
MII_MD<1:0>
CFG<2:0>
ADDR<4:2>
MDIO
MDC
MDINT
Management /
Mode Select
Logic
MII Power
Supply
3.3V or 5V
Global Functions
Internal Clocks
Pwr Supply /
PwrDown
CLK25M
VCC
GND
PWRDN
RESET
SerLED
LEDENA
LEDCLK
LEDDAT
T P O P / F I B I Nn
/
Fiber In
T P O N / F I B I Pn
3
Register Set
T X _ E Nn
MII
T X _ E Rn
T X Dn < 3 : 0 >
Parallel/Serial
Converter
Manchester
10
Encoder
Scrambler
100
& Encoder
Auto
Negotiation
Tristate Control
Pulse
Shaper
TP
Driver
+
TP Out
-
+
-
ECL
Driver
T R S T En
T X _ C L Kn
R X _ C L Kn
FDX Status
& LED
Drivers
Clock
Generator
Manchester
Decoder
Decoder &
Descrambler
Media Select &
Line Energy Monitor
TP
Rcvr
3
L E Dn < 2 : 0 >
S D / T Xn
+
-
Fiber Out
T P I P / F I B O Pn
/
TP In
T P I N / F I B O Nn
MII
RXDn<3:0>
C R Sn
C O Ln
R X _ D Vn
R X _ E Rn
Carrier Sense
Collision Detect
Data Valid
Error Detect
Serial to
Parallel
Converter
10
100
Slicer
Baseline
Wander
Correction
ECL
Rcvr
PORT 0
PORT 1
PORT 2
PORT 3
+
-
Per-Port Functions
Refer to www.level1.com for current product information.
LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver
TABLE OF CONTENTS
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS ................................................................... 4
FUNCTIONAL DESCRIPTION ..................................................................................................... 14
Introduction .............................................................................................................................. 14
Network Media/Protocol Support ............................................................................................. 15
10/100 Mbps Network Interface.......................................................................................... 15
Twisted-Pair Interface.................................................................................................... 15
Fiber Interface ............................................................................................................... 15
MII Interface........................................................................................................................ 16
MII Data Interface .......................................................................................................... 16
Loopback ....................................................................................................................... 17
MII Management Interface............................................................................................. 18
MII Interrupts ....................................................................................................... 18
Hardware Control Interface................................................................................................. 19
Initialization .............................................................................................................................. 21
MDIO Control Mode............................................................................................................ 21
Manual Control Mode ......................................................................................................... 21
Link Configuration............................................................................................................... 21
Auto-Negotiation ...................................................................................................................... 22
100 Mbps Operation ................................................................................................................ 23
4B/5B Coding Table ............................................................................................................ 24
100BASE-X Protocol Sublayer Operations......................................................................... 25
10 Mbps Operation .................................................................................................................. 28
LED Functions ......................................................................................................................... 29
Serial LED Output............................................................................................................... 29
Per-Port LEDs..................................................................................................................... 29
Operating Requirements.......................................................................................................... 30
Power Requirements .......................................................................................................... 30
Clock Requirements ........................................................................................................... 30
APPLICATION INFORMATION ................................................................................................... 31
Design Recommendations....................................................................................................... 31
Power Supply Filtering........................................................................................................ 31
Power and Ground Plane Layout Considerations............................................................... 32
Twisted-Pair and Fiber Interfaces ....................................................................................... 33
Magnetics Information ........................................................................................................ 34
Magnetics With Improved Return Loss Performance .................................................... 34
Typical Application Circuitry ..................................................................................................... 36
2
LXT974A/LXT975A Table of Contents
TEST SPECIFICATIONS .............................................................................................................. 42
Absolute Maximum Ratings ................................................................................................ 42
Operating Conditions .......................................................................................................... 42
Digital I/O Characteristics.................................................................................................... 43
Digital I/O Characteristics - MII Pins ................................................................................... 43
Required CLK25M Characteristics ...................................................................................... 43
Low-Voltage Fault Detect Characteristics ........................................................................... 44
100BASE-TX Transceiver Characteristics .......................................................................... 44
100BASE-FX Transceiver Characteristics .......................................................................... 45
10BASE-T Transceiver Characteristics............................................................................... 45
MII-100BASE-TX Receive Timing ...................................................................................... 46
MII-100BASE-TX Transmit Timing ..................................................................................... 47
MII-100BASE-FX Receive Timing ....................................................................................... 48
MII-100BASE-FX Transmit Timing ...................................................................................... 49
MII-10BASE-T Receive Timing ........................................................................................... 50
MII-10BASE-T Transmit Timing........................................................................................... 51
10BASE-T SQE (Heartbeat) Timing.................................................................................... 52
10BASE-T Jab and Unjab Timing ....................................................................................... 52
Auto Negotiation and Fast Link Pulse Timing ..................................................................... 53
MDIO and MII Timing .......................................................................................................... 54
Reset and Power-Down Recovery Timing .......................................................................... 55
Serial LED Timing ............................................................................................................... 55
REGISTER DEFINITIONS ............................................................................................................ 56
Control Register (Address 0)............................................................................................... 57
Status Register (Address 1) ................................................................................................ 58
PHY Identification Register 1 (Address 2)........................................................................... 59
PHY Identification Register 2 (Address 3)........................................................................... 59
Auto Negotiation Advertisement Register (Address 4)........................................................ 60
Auto Negotiation Link Partner Ability Register (Address 5)................................................. 61
Auto Negotiation Expansion (Address 6) ............................................................................ 62
LED Configuration Register (Address 16, hex 10) .............................................................. 63
Interrupt Enable Register (Address 17, hex 11) .................................................................. 64
Interrupt Status Register (Address 18, hex 12) ................................................................... 64
Port Configuration Register (Address 19, hex 13) .............................................................. 65
Port Status Register (Address 20, hex 14).......................................................................... 66
PACKAGE SPECIFICATION........................................................................................................ 67
REVISION HISTORY .................................................................................................................... 68
3
LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT974 Pin Assignments
LED3_0 ..... 1
LED3_1 ..... 2
LED3_2 ..... 3
LED2_0 ..... 4
LED2_1 ..... 5
LED2_2 ..... 6
GND ..... 7
LED1_0 ..... 8
LED1_1 ..... 9
LED1_2 ..... 10
LED0_0 ..... 11
LED0_1 ..... 12
LED0_2 ..... 13
GND ..... 14
LEDCLK ..... 15
LEDDAT ..... 16
LEDENA ..... 17
ADD2 ..... 18
ADD3 ..... 19
ADD4 ..... 20
GNDA ..... 21
VCC ..... 22
RXD0_3 ..... 23
RXD0_2 ..... 24
RXD0_1 ..... 25
RXD0_0 ..... 26
RX_DV0 ..... 27
RX_CLK0 ..... 28
RX_ER0 ..... 29
TX_ER0 ..... 30
TX_CLK0 ..... 31
TX_EN0 ..... 32
TXD0_0 ..... 33
TXD0_1 ..... 34
TXD0_2 ..... 35
TXD0_3 ..... 36
COL0 ..... 37
CRS0 ..... 38
GND ..... 39
VCCMII ..... 40
N/C...................41
RXD1_3............42
RXD1_2............43
RXD1_1............44
RXD1_0............45
RX_DV1 ...........46
RX_CLK1.........47
RX_ER1 ...........48
TX_ER1 ...........49
TX_CLK1.........50
TX_EN1 ...........51
TXD1_0............52
TXD1_1............53
TXD1_2............54
TXD1_3............55
GND.................56
COL1................57
CRS1 ................58
GND.................59
VCC..................60
RXD2_3............61
RXD2_2............62
RXD2_1............63
RXD2_0............64
RX_DV2 ...........65
RX_CLK2.........66
RX_ER2 ...........67
TX_ER2 ...........68
TX_CLK2.........69
TX_EN2 ...........70
TXD2_0............71
TXD2_1............72
TXD2_2............73
TXD2_3............74
COL2................75
CRS2 ................76
GND.................77
VCCMII ...........78
RXD3_3............79
RXD3_2............80
160 ... GND
159 ... TEST
158 ... SD0/TP0
157 ... TPON/FIBIP0
156 ... VCCT
155 ... GNDT
154 ... TPOP/FIBIN0
153 ... VCCR
152 ... TPIN/FIBON0
151 ... TPIP/FIBOP0
150 ... GNDR
149 ... SD1/TP1
148 ... TPON/FIBIP1
147 ... VCCT
146 ... GNDT
145 ... TPOP/FIBIN1
144 ... VCCR
143 ... TPIN/FIBON1
142 ... TPIP/FIBOP1
141 ... GNDR
140 ... RBIAS
139 ... SD2/TP2
138 ... TPON/FIBIP2
137 ... VCCT
136 ... GNDT
135 ... TPOP/FIBIN2
134 ... VCCR
133 ... TPIN/FIBON2
132 ... TPIP/FIBOP2
131 ... GNDR
130 ... SD3/TP3
129 ... TPON/FIBIP3
128 ... VCCT
127 ... GNDT
126 ... TPOP/FIBIN3
125 ... VCCR
124 ... TPIN/FIBON3
123 ... TPIP/FIBOP3
122 ... GNDR
121 ... GNDR
(Date Code)
(Part#)
XXXX XXXX
LXT974AHC or
LXT974QC
XXXXXX
(Lot#)
120 ........ N/C
119 ........ N/C
118 ........ CLK25M
117 ........ FDE_FX
116 ........ CFG_0
115 ........ CFG_1
114 ........ CFG_2
113 ........ BYPSCR
112 ........ TEST
111 ........ AUTOENA
110 ........ FDE
109 ........ RESET
108 ........ GNDH
107 ........ VCCH
106 ........ TRSTE0
105 ........ TRSTE1
104 ........ TRSTE2
103 ........ TRSTE3
102 ........ PWRDN
101 ........ TEST
100 ........ MDDIS
99 .......... MDC
98 .......... MDINT
97 .......... MDIO
96 .......... VCC
95 .......... GND
94 .......... CRS3
93 .......... COL3
92 .......... TXD3_3
91 .......... TXD3_2
90 .......... TXD3_1
89 .......... TXD3_0
88 .......... TX_EN3
87 .......... TX_CLK3
86 .......... TX_ER3
85 .......... RX_ER3
84 .......... RX_CLK3
83 .......... RX_DV3
82 .......... RXD3_0
81 .......... RXD3_1
4
LXT974A/LXT975A Pin Assignments and Signal Descriptions
Table 1: LXT974A Signal Detect/TP Select Signal Descriptions
Pin#
2
158
149
139
130
Symbol
SD0/TP0
SD1/TP1
SD2/TP2
SD3/TP3
Type
1
I
Signal Description
Signal Detect - Ports 0 - 3.
When SD/TPn pins are tied High or to a 5V PECL input,
bit 19.2 = 1 and the operating mode of each respective port is forced to FX mode. In
this mode, full-duplex is set via pin 117 (FDE_FX). When not using FX mode, SD/
TPn pins should be tied to GNDT.
TP Select - Ports 0 - 3.
When SD/TPn pins are tied Low, bit 19.2 = 0. The operating
mode of each port can be set to 10BASE-T, 100BASE-TX, or 100BASE-FX via the
hardware control interface pins as shown in Table 8 on page 11.
Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and
AUTOENA) are global and set all ports simultaneously.
In TP mode, network pins operate as described in Table 2.
In FX mode, network pins are re-mapped and operate as described in Table 3.
1. Type Column Coding: I = Input, O = Output.
2. When not using fiber mode, SD/TPn pins should be tied to GNDT.
Table 2: LXT974A Twisted-Pair Interface Signal Descriptions
Pin#
154, 157
145, 148
135, 138
126, 129
151, 152
142, 143
132, 133
123, 124
Symbol
TPOP0, TPON0
TPOP1, TPON1
TPOP2, TPON2
TPOP3, TPON3
TPIP0, TPIN0
TPIP1, TPIN1
TPIP2, TPIN2
TPIP3, TPIN3
Type
1
O
Signal Description
Twisted-Pair Outputs, Positive & Negative - Ports 0-3.
During 100BASE-TX or 10BASE-T operation, TPO pins drive 802.3
compliant pulses onto the line.
I
Twisted-Pair Inputs, Positive & Negative - Ports 0-3.
During 100BASE-TX or 10BASE-T operation, TPI pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
1. Type Column Coding: I = Input, O = Output.
Table 3: LXT974A Fiber Interface Signal Descriptions
Pin#
154, 157
145, 148
135, 138
126, 129
151, 152
142, 143
132, 133
123, 124
Symbol
FIBIN0, FIBIP0
FIBIN1, FIBIP1
FIBIN2, FIBIP2
FIBIN3, FIBIP3
FIBOP0, FIBON0
FIBOP1, FIBON1
FIBOP2, FIBON2
FIBOP3, FIBON3
Type
1
I
Signal Description
Fiber Inputs, Positive & Negative - Ports 0-3.
During 100BASE-FX operation, FIBI pins receive differential PECL
inputs from fiber transceivers.
O
Fiber Outputs, Positive & Negative - Ports 0-3.
During 100BASE-FX operation, FIBO pins produce differential
PECL outputs for fiber transceivers.
1. Type Column Coding: I = Input, O = Output.
5
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