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TSB21LV03C
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS331A – FEBRUARY 1999 – REVISED OCTOBER 1999
D
D
D
D
D
D
D
D
D
D
Fully Supports Provisions of IEEE
1394-1995 Standard for High Performance
Serial Bus
Fully Interoperable with FireWire™ and
i.LINK™ Implementation of IEEE 1394-1995
Provides Three Fully Compliant Cable
Ports at 100/200 Megabits per Second
(Mbits/s)
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Device Power-Down Feature to Conserve
Energy in Battery-Powered Applications
Inactive Ports Disabled to Save Power
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
Incoming Data Resynchronized to Local
Clock
Single 3.3-V Supply Operation
D
D
D
D
D
D
D
D
D
Interface to Link-Layer Controller Supports
Low Cost TI™ Bus-Holder Isolation
Data Interface to Link-Layer Controller
Provided Through 2/4 Parallel Lines at
49.152 MHz
Low Cost 24.576-MHz Crystal Oscillator
and PLL Provide Transmit/Receive Data at
100/200 Mbits/s, and Link-Layer Controller
Clock at 49.152 MHz
Interoperable with 1394 Link-Layer
Controllers Using 5-V Supplies
Interoperable Across 1394 Cable with 1394
Physical Layers (Phy) Using 5-V Supplies
Node Power-Class Information Signaling
for System Power Management
Cable Power Presence Monitoring
Separate Cable Bias and Driver Termination
Voltage Supply for Each Port
High Performance 64-Pin TQFP (PM)
Package and 68-Pin CFP (HV) Package
description
The TSB21LV03C provides the analog and digital physical layer functions needed to implement a three-port
node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers.
The transceivers include circuitry to monitor the line conditions as needed for determining connection status,
for initialization and arbitration, and for packet reception and transmission. The TSB21LV03C is designed to
interface with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, TSB12C01, TSB12LV22,
TSB12LV41, or TSB12LV01.
The TSB21LV03C requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The
196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control
transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also
supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the
received data. For the TSB21LV03C, the 49.152 MHz clock output is active when RESET is asserted low. The
power-down function, when enabled by taking the PD terminal high, stops operation of the PLL and disables
all circuitry except the cable-not-active signal circuitry.
The TSB21LV03C supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the
link interface outputs behave normally. Also, when ISO is tied high, the internal bus hold function is enabled for
use with the TI Bus Holder isolation. TI bus holder isolation is implemented when ISO is tied high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Incorporated.
i.LINK is a trademark of SONY.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TSB21LV03C
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS331A – FEBRUARY 1999 – REVISED OCTOBER 1999
description (continued)
Data bits to be transmitted through the cable ports are received from the LLC on two or four data lines (D0 –
D3), and are latched internally in the TSB21LV03C in synchronization with the 49.152-MHz system clock. These
bits are combined serially, encoded, and transmitted at 98.304 or 196.608 Mbits/s as the outbound data-strobe
information stream. During transmission, the encoded data information is transmitted differentially on the TPB
cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
Strobe information is received on the TPB cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial data bits are split into two or four parallel
streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also
transmitted (repeated) out of the other active (connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied
twisted-pair bias voltage. The presence or absence of this common-mode voltage is used as an indication of
cable connection status. The cable connection status signal is internally debounced in the TSB21LV03C on a
cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. On a cable
disconnect-to-connect a debounce delay is incorporated. There is no delay on a cable disconnect.
The TSB21LV03C provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability between transceiver chips operating from either 5-V or
3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of
approximately 1.0
µF.
The transmitter circuitry is disabled under the following conditions: power down, cable not active, reset, or
transmitter disable. The receiver circuitry is disabled under the following conditions: power down, cable not
active, or receiver disable. The twisted-pair bias voltage circuitry is disabled under the following conditions:
power down or reset. The power-down condition occurs when the PD input is high. The cable-not-active (CNA)
condition occurs when the cable connection status indicates that no cable is connected. The reset condition
occurs when the RESET input terminal is low. The transmitter disable and receiver disable conditions are
determined from the internal logic.
The line drivers in the TSB21LV03C operate in a high-impedance current mode and are designed to work with
external 110-Ω line-termination resistor networks. One network is provided at each end of each twisted-pair
cable. Each network is composed of a pair of series-connected 55-Ω resistors. The midpoint of the pair of
resistors that is directly connected to the twisted-pair A (TPA) package terminals is connected to the TPBIAS
voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB)
package terminals is coupled to ground through a parallel RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF respectively. The values of the external resistors are designed to meet the draft
standard specifications when connected in parallel with the internal receiver circuits and are shown in
Figure 3.
The driver output current, along with other internal operating currents, is set by an external resistor. This resistor
is connected between the R0 and R1 terminals and has a value of 6.3 kΩ,
±0.5%.
This might be accomplished
by placing a 6.34 kΩ,
±0,5%
resistor in parallel with a 1-MΩ resistor.
2
POST OFFICE BOX 655303
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TSB21LV03C
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS331A – FEBRUARY 1999 – REVISED OCTOBER 1999
description (continued)
Four package terminals are used as inputs to set four configuration status bits in the self-identification (Self-ID)
packet. These terminals are hardwired high or low as a function of the equipment design. PC0 – PC2 are the
three terminals that indicate either the need for power from the cable or the ability to supply power to the cable.
The fourth terminal, C/LKON, indicates whether a node is a contender for bus manager. When the C/LKON
terminal is asserted, it means the node can be a contender for bus manager. When the terminal is not asserted,
it means that the node is not a contender. The C bit corresponds to bit 20 in the Self-ID packet, PC0 corresponds
to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see Table 4–29 of the IEEE 1394–1995
standard for additional details).
A power-down terminal, PD, is provided to allow a power-down mode where most of the TSB21LV03C circuits
are powered down to conserve energy in battery-powered applications. A cable status terminal, CNA, provides
a high output when all twisted-pair cable ports are disconnected. This output is not debounced. The CNA output
can be used to determine when to power the TSB21LV03C down or up. In the power-down mode all circuitry
is disabled except the CNA circuitry. It should be noted that when the device is powered-down it does not act
in a repeater mode. When the TSB21LV03C is powered down using the PD terminal, the twisted-pair transmitter
and receiver circuitry has been designed to present a high impedance to the cable to prevent loading the TPBias
terminal voltage on the other end of the cable.
NOTE:
Reference suspend/resume section in the current 1394a specification for interoperability with PD
implementation of power down.
If the TSB21LV03C is being used with one or more of the ports not being brought out to a connector, the TPB
terminals must be terminated for reliable operation. For each unused port, the TPB+ and TPB– terminals must
be connected to GND. This is done in the normal termination network. When a port does not have a cable
connected, the normal termination network pulls TPB+ and TPB– to ground through a 5-kΩ resistor, thus
disabling the port.
NOTE:
All gap counts on all nodes of a 1394 bus must be identical. This may only be accomplished by using
phy configuration packets (see section 4.3.4.3 of IEEE 1394-1995 Standard) or by using two bus
resets, which resets the gap counts to the maximum level (3 Fh).
The link power status (LPS) terminal works with the C/LKON terminal to manage the LLC power usage of the
node. The LPS terminal indicates that the LLC of the node is powered down and powers down the phy-LLC
interface to save power. If the phy then receives a link-on packet, the C/LKON terminal is activated to output
a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the LPS
signal communicates this to the TSB21LV03C and the C/LKON signal is turned off and the phy-link interface
is enabled.
Two of the package terminals are used to set up various test conditions used in manufacturing. These terminals,
TESTM1 and TESTM2, should be connected to V
DD
for normal operation.
The TSB21LV03C is characterized for operation from 0°C to 70°C. The TSB21LV03CI is characterized for
operation from – 40°C to 85°C. The TSB21LV03CM is characterized for operation over the full military
temperature range of – 55°C to 125°C.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
3
TSB21LV03C
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS331A – FEBRUARY 1999 – REVISED OCTOBER 1999
functional block diagram
CPS
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
Arbitration
and
Control
State
Machine
Logic
Link
Interface
I/O
Received
Data
Decoder/
Retimer
Bias
Voltage
and
Current
Generator
R0
R1
TPBIAS1
TPBIAS2
TPBIAS3
TPA 1+
TPA1 –
PC0
PC1
PC2
C/LKON
TESTM1
TESTM2
Cable Port 1
TPB1 +
TPB1 –
TPA2 +
PD
Transmit
Data
Encoder
Cable Port 2
TPA2 –
TPB2 +
TPB2 –
RESET
TPA3 +
Cable Port 3
TPA3 –
TPB3 +
TPB3 –
Crystal
Oscillator,
PLL
System, and
Clock
Generator
XI
XO
FILTER
4
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