TC74VHC573F(EL,F) datasheet, PDF

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TC74VHC573F(EL,F): DescriptionIC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,SOP,20PIN,PLASTIC; Categorylogic logic; File Size202KB，10 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/; Environmental Compliance

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TC74VHC573F(EL,F) Overview

IC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,SOP,20PIN,PLASTIC

TC74VHC573F(EL,F) Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Toshiba Semiconductor
package instruction	SOP, SOP20,.3
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G20
Load capacitance (CL)	50 pF
Logic integrated circuit type	D LATCH
MaximumI(ol)	0.008 A
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
power supply	2/5.5 V
Prop。Delay @ Nom-Sup	10 ns
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Base Number Matches	1

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TC74VHC573F/FT/FK

TOSHIBA CMOS Digital Integrated Circuit

Silicon Monolithic

TC74VHC573F,TC74VHC573FT,TC74VHC573FK

Octal D-Type Latch with 3-State Output

The TC74VHC573 is an advanced high speed CMOS OCTAL

LATCH with 3-STATE OUTPUT fabricated with silicon gate

C2MOS technology.

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low power

dissipation.

This 8-bit D-type latch is controlled by a latch enable input

(LE) and an output enable input (

When the

input is high, the eight outputs are in a high

impedance state.

An input protection circuit ensures that 0 to 5.5 V can be

applied to the input pins without regard to the supply voltage.

This device can be used to interface 5 V to 3 V systems and two

supply systems such as battery back up. This circuit prevents

device destruction due to mismatched supply and input voltages.

TC74VHC573F

TC74VHC573FT

Features

•

High speed: t

= 4.5 ns (typ.) at V

5 V

Low power dissipation: I

μA

(max) at Ta

25°C

High noise immunity: V

NIH

NIL

28% V

(min)

Power down protection is provided on all inputs.

Balanced propagation delays: t

pLH

∼

pHL

−

Wide operating voltage range: V

CC (opr)

2 to 5.5 V

Low noise: V

OLP

1.2 V (max)

Pin and function compatible with 74ALS573

TC74VHC573FK

Weight

SOP20-P-300-1.27A

TSSOP20-P-0044-0.65A

VSSOP20-P-0030-0.50

: 0.22 g (typ.)

: 0.08 g (typ.)

: 0.03 g (typ.)

2007-10-01

TC74VHC573F(EL,F) Related Products

	TC74VHC573F(EL,F)	TC74VHC573FT(EL,M)	TC74VHC573F(F)	TC74VHC573FK(EL)
Description	IC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,SOP,20PIN,PLASTIC	IC AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, 0.65 MM PITCH, PLASTIC, TSSOP-20, Bus Driver/Transceiver	IC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,SOP,20PIN,PLASTIC	IC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,TSSOP,20PIN,PLASTIC
package instruction	SOP, SOP20,.3	TSSOP,	SOP, SOP20,.3	TSSOP, TSSOP20,.16,20
Reach Compliance Code	unknown	unknown	unknown	unknown
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
Logic integrated circuit type	D LATCH	BUS DRIVER	D LATCH	D LATCH
Number of digits	8	8	8	8
Number of functions	1	1	1	1
Number of terminals	20	20	20	20
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maker	Toshiba Semiconductor	-	Toshiba Semiconductor	Toshiba Semiconductor
Load capacitance (CL)	50 pF	-	50 pF	50 pF
MaximumI(ol)	0.008 A	-	0.008 A	0.008 A
Encapsulate equivalent code	SOP20,.3	-	SOP20,.3	TSSOP20,.16,20
power supply	2/5.5 V	-	2/5.5 V	2/5.5 V
Prop。Delay @ Nom-Sup	10 ns	-	10 ns	10 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Base Number Matches	1	1	1	-

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