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HD74ALVCH16836TEL

Description
Bus Driver, 1-Func, 20-Bit, True Output, CMOS, PDSO56
Categorylogic    logic   
File Size55KB,13 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HD74ALVCH16836TEL Overview

Bus Driver, 1-Func, 20-Bit, True Output, CMOS, PDSO56

HD74ALVCH16836TEL Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
package instructionTSSOP, TSSOP56,.3,20
Reach Compliance Codeunknown
Control typeENABLE LOW
JESD-30 codeR-PDSO-G56
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Number of digits20
Number of functions1
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply3.3 V
Prop。Delay @ Nom-Sup3.6 ns
Certification statusNot Qualified
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Base Number Matches1
HD74ALVCH16836
20-bit Universal Bus Driver with 3-state Outputs
ADE-205-213 (Z)
Preliminary
1st. Edition
January 1998
Description
This 20-bit universal bus driver is designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (O
E)
input. The device operates in the
transparent mode when the latch enable (LE) input is low. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If
LE
is high, the A data is stored in the latch flip flop on the low to high
transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating inputs at a valid logic level.
Features
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±24 mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
ad/da
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