70V7339S133BFG datasheet, PDF - EEWORLD Datasheet

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70V7339S133BFG: DescriptionDual-Port SRAM, 512KX18, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208; Categorystorage storage; File Size224KB，21 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V7339S133BFG Overview

Dual-Port SRAM, 512KX18, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208

70V7339S133BFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	4.2 ns
Other features	PIPELINED ARCHITECTURE OR FLOW-THROUGH
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	9437184 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
Base Number Matches	1

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HIGH-SPEED 3.3V 512K x 18

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

IDT70V7339S

◆

512K x 18 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 8K x 18 banks

– 9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in 208-pin fine pitch Ball Grid Array (fpBGA) and

256-pin Ball Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

8Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-17L

I/O

CONTROL

MUX

8Kx18

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-17R

12L

ADDRESS

DECODE

ADDRESS

DECODE

12R

BANK

DECODE

MUX

8Kx18

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 18

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5628 drw 01

APRIL 2010

DSC 5628/9

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