AIMM
M832G0115AP0 SGRAM AGP In-Line Memory Module
M832G0115AP0
1Mx32 SGRAM AIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
GENERAL DESCRIPTION
The Samsung M832G0115AP is a 1M bit x 32 Synchro-
nous Graphic RAM based AGP in-line memory module.
The Samsung M832G0115AP consists of one 1M x 32 bit
Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 132pin glass-epoxy substrate. The
M832G0115AP is a AGP In-line Memory Module and is
intended for mounting into 132-pin edge connector sock-
ets(AGP socket).
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies, pro-
grammable latencies and burst lengths allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
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FEATURE
• Performance range
Part NO.
M832G0115AP0-C7C
M832G0115AP0-C70
Frequency (t
CC
min)
133MHz (7.5ns) @CL=2, tRCD/tRP=2CLK
133MHz (7.0ns) @CL=3, tRCD/tRP=3CLK
* M832G0115AP0 : based on PQFP Component
Burst Mode Operation
Independent byte operation via DQM0 ~ 3
Auto & Self Refresh Capability (2048 cycles / 32ms)
LVTTL compatible inputs and outputs
Single 3.3V±0.3V power supply
MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• Resistor Strapping Options for speed
• PCB : Height 1,400mil, single sided components
PIN CONFIGURATIONS (B Side / A Side)
Pin
B
Pin
A
Pin
B
KEYWAY
KEYWAY
KEYWAY
DQ21
DQ20
Vcc
DQ19
DQ18
GND
NC
DQ17
V
DDQ
DQ16
DQ15
GND
DQ14
DQ13
V
DDQ
DQ12
NC
GND
NC
MODULE PIN NAMES
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
KEYWAY
KEYWAY
KEYWAY
CLK0
CLK1*
Vcc
CAS
NC
GND
NC
RAS
V
DDQ
A0
A9
GND
A11
A10
V
DDQ
A8/AP*
NC
GND
B
V
CC
DQ11
V
DDQ
NC
GND
NC
DQ10
V
DDQ
DQ9
DQ8
GND
DQM1
DQ0
V
DDQ
NC
DQ1
GND
DQ2
DQ3
V
DDQ
DQ4
NC
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
A
Vcc
A7
CS
NC
GND
A6
A1
V
DDQ
A5
A2
GND
A4
A3
V
DDQ
NC
DQ5
GND
DQ6
DQ7
V
DDQ
DQM0
NC
Pin Name
A0~A10
A11
DQ0 ~ DQ31
CLK0,CLK1*
CS
CKE
RAS
CAS
WE
DQM
V
cc
V
ddq
GND
NC
KEYWAY*
FSEL*
TYPEDET*
Function
Address Input (multiplexed)
SDRAM Bank Select (BA)
Data Inputs / Outputs
Clock Input
Chip Select Input
CLK Enable
Row Address Storbe
Colume Address Strobe
Write Enable
DQ Mask Enable
Power Supply
Power supply for Data In/Out
Ground(Vss)
No Connection
KEYWAY
Memory Frequency Select
TYPEDET
NC
1
NC
2
NC
3
NC
4
GND
5
NC
6
NC
7
DQ27
8
Vcc
9
DQ28
10
DQ29
11
DQ30
12
GND
13
NC
14
DQ31
15
Vcc
16
DQM2
17
NC
18
GND
19
DQ23
20
DQ22
21
22 KEYWAY
NC
1
23
2 TYPEDET 24
NC
3
25
NC
4
26
GND
5
27
NC
6
28
NC
7
29
NC
8
30
Vcc
9
31
DQM3
10
32
NC
11
33
DQ24
12
34
GND
13
35
NC
14
36
DQ25
15
37
Vcc
16
38
DQ26
17
39
NC
18
40
GND
19
41
WE
20
42
21
43
FSEL
22 KEYWAY 44
NC
* These pins are not used in this module
and should be NC
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
-3-
Rev. 1.0 (Jul. 2000)
AIMM
COMPONENT PIN CONFIGURATION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs.
M832G0115AP0
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Not used. Must Connected to low
Power Supply : +3.3V
±
0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
No connection
CKE
Clock Enable
A0 ~ A10
BA
RAS
CAS
WE
DQMi
DQi
DSF
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
-4-
Rev. 1.0 (Jul. 2000)
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