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MT47H64M8JN-25EAAT:G

Description
DDR DRAM, 64MX8, 0.45ns, CMOS, PBGA60, 8 X 10 MM, FBGA-60
Categorystorage    storage   
File Size2MB,129 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT47H64M8JN-25EAAT:G Overview

DDR DRAM, 64MX8, 0.45ns, CMOS, PBGA60, 8 X 10 MM, FBGA-60

MT47H64M8JN-25EAAT:G Parametric

Parameter NameAttribute value
MakerMicron Technology
Parts packaging codeBGA
package instructionTFBGA,
Contacts60
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.45 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B60
length10 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals60
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
organize64MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width8 mm
Base Number Matches1
Micron Confidential and Proprietary
512Mb: x8, x16 Automotive DDR2 SDRAM
Features
Automotive DDR2 SDRAM
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
Features
Industrial and automotive temperature compliant
V
DD
= 1.8V ±0.1V, V
DDQ
= 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
32ms, 8192-cycle refresh
On-die termination (ODT)
RoHS-compliant
Supports JEDEC clock jitter specification
AEC-Q100
PPAP submisson
8D response time
Options
1
• Configuration
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• FBGA package (Pb-free) – x8
– 60-ball FBGA (8mm x 10mm)
• FBGA package (Pb-free) – x16
– 84-ball FBGA (8mm x 12.5mm)
• FBGA package (lead solder) – x8
– 60-ball FBGA (8mm x 10mm)
• FBGA package (lead solder) – x16
– 84-ball FBGA (8mm x 12.5mm)
• Timing – cycle time
– 2.5ns @ CL = 5 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
• Self refresh
– Standard
– Low-power
• Operating temperature
– Industrial (–40°C T
C
+95°C;
–40°C T
A
+85°C)
– Automotive (–40°C T
C
, T
A
+105ºC)
• Revision
Note:
Marking
64M8
32M16
CF
HR
JN
HW
-25E
-3
None
L
AIT
AAT
:G
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed Grade
-25E
-25
-3E
-3
CL = 3
400
400
400
400
CL = 4
533
533
667
533
CL = 5
800
667
667
667
CL = 6
800
800
n/a
n/a
CL = 7
n/a
n/a
n/a
n/a
t
RC
(ns)
55
55
54
55
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹
2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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