QS7203, QS7204
Q
FEATURES
•
•
•
•
•
High-Speed CMOS
High Speed CMOS
2K x
Bus Exchange
9, 4K x 9 FIFO
Buffer
Switches
Memories
•
•
•
•
QS3383
QS7203
QS32383
QS7204
1
2
10-ns flag and data access times
Fully asynchronous read and write
Zero fall-through time
Expandable in depth with no speed loss
TTL compatible input and output levels
Low power with industry standard pinouts
Retransmit capability
Dual-port RAM-based cell technology
Available in PDIP, SOJ, SOIC, and PLCC
DESCRIPTION
The QS7203 and QS7204 are 2K x 9 and 4K x 9 FIFOs, respectively. These FIFOs use a dual-port RAM-based
architecture and have independent read and write pointers. This allows high speed with zero fall-through time.
The read and write pointers are incremented on the rising edges of the read and write lines. The flag circuitry
is based on a patented high-speed design, giving precise half-full, full, and empty conditions. These flags also
prevent the FIFO from being written into when full or being read from when empty. These FIFOs are easily
cascadable to any depth and expandable to any width without any speed penalty. Retransmit resets the read
pointer to memory location zero and is useful for data communications, digital filtering, and video line-doubling
applications.
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
DATA IN
D8-D0
W
R
RS
FL
/
RT
XI
WRITE
CONTROL
READ
CONTROL
RESET
LOGIC
EXPANSION
LOGIC
WRITE
POINTER
READ
POINTER
DUAL-PORT
RAM ARRAY
2K x 9
4K x 9
FLAG
LOGIC
EF
FF
HF
XO
DATA OUT
Q8-Q0
Note:
XO
and
HF
share the same pin, so the Half-Full flag is available only in standalone, not depth-expansion mode.
MDSF-00002-04
APRIL 28, 1995
QUALITY SEMICONDUCTOR, INC.
1
QS7203, QS7204
FIGURE 2. PINOUTS (All pins top view)
PDIP, SOIC, SOJ
D3
D8
PLCC
VCC
NC
D4
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL
/
RT
RS
EF
XO HF
INDEX
D2
D1
D0
5
6
7
4
3
2
1
32
31
D5
W
30
29
28
27
26
25
24
23
22
21
D6
D7
NC
XI
8
/
FL
/
RT
RS
EF
XO
/
HF
Q7
Q6
FF
9
Q0
Q1
NC
Q2
10
11
12
13
14
Q3
Q7
Q6
Q5
Q4
R
15
Q8
16
GND
17
NC
18
19
Q4
20
Q5
PIN DESCRIPTIONS
Name
Di
Qi
I/O
I
O
I
I
O
O
I
I
I
O
Description
Data Inputs
Data Outputs
Read Clock
Write Clock
Empty Flag
Full Flag
Reset
First Load/Retransmit
Expansion Clock In
Expansion Clock Out/
Half-Full Flag
R
W
EF
FF
RS
FL
/
RT
XI
XO
/
HF
2
QUALITY SEMICONDUCTOR, INC.
R
MDSF-00002-04
APRIL 28, 1995
QS7203, QS7204
OPERATIONAL DESCRIPTION AND APPLICATION INFORMATION
The QS7203 and QS7204 are 2K x 9 and 4K x 9 FIFOs, respectively. These FIFOs use a dual-port RAM-based
architecture and have independent read and write pointers. This allows high speed with zero fall-through time.
The write line causes data to be written into the FIFO. The read line causes data to be read from the FIFO.
The read line also activates the three-state outputs to present the read data. The read and write pointers are
incremented on the rising edges of the read and write lines. The flag circuitry is based on a reliable sequential
design giving precise half-full, full, and empty conditions. These flags also prevent the FIFO from being written
into when full or being read from when empty. Depth expansion pins are provided, which allow these FIFOs
to be expanded in depth without speed penalty. Retransmit capability is provided. Activating the retransmit
pin resets the read pointer to zero and is useful for data communications and digital filtering applications.
1
2
SIGNAL DESCRIPTION
DATA INPUTS
D8-D0
The data in lines D8 to D0 provide data to be written into the FIFO.
Note:
Unused inputs must be tied to Vcc or GND.
CONTROL INPUTS
Reset (
RS
)
The reset input resets the read and write pointers and the flags to zero. The FIFO must be reset at power-up
to ensure proper operation of the pointers and flags. This is done by asserting the reset line to a LOW state,
which causes the FIFO flags to be set to empty. This causes the Empty flag to be asserted and the Full and
Half-Full flags to be de-asserted. Read and write lines must be HIGH for t
RSS
before and t
RSR
after the rising
edge of the reset signal for a valid reset operation.
Write (
W
)
The write line causes data to be written into the FIFO. A write cycle is initiated by the falling edge of the write
signal. A write will occur if the Full flag was not asserted, indicative of at least one empty location in the FIFO.
Data is stored in the FIFO on the rising edge of the write signal, using the data setup and hold times specified.
Data is stored in a sequential manner in the FIFO, and the read and write operations can be asynchronous.
The falling edge of the write signal asserts the Half-Full and Full flags when the next word after half-full is written
and when the last word has been written, respectively. The rising edge of the write line de-asserts the Empty
flag when the first write is performed after an empty or reset condition. When the Full flag is asserted,
subsequent writes are blocked. The user can apply a write pulse after the full condition is de-asserted.
Read (
R
)
The read signal causes data to be read from the FIFO. A read cycle is initiated by the falling edge of the read
signal. A read is performed if the Empty flag is not asserted, indicative of at least one word being present in
the FIFO. The data is accessed on a first-in-first-out basis asynchronous to the write operations. After the read
control is de-asserted, the data outputs go from a valid state into high impedance. The outputs remain in high
impedance until the next read cycle. When all the data is read on the last read cycle, the Empty flag is asserted,
and will inhibit any subsequent reads. The outputs will be in high impedance for subsequent read operation
until a write occurs that de-asserts the Empty flag, allowing a read cycle to begin. The outputs may also be
in high impedance when the FIFOs are cascaded in depth. In this case, only the active FIFO asserts data, and
the other FIFO data outputs are in high impedance. The falling edge of the read signal will set the Empty flag
during the read of the last word in the FIFO. The rising edge of the read signal will de-assert the Half-Full and
the Full flags when the FIFO has reached half-full and when the FIFO is full, respectively.
MDSF-00002-04
APRIL 28, 1995
QUALITY SEMICONDUCTOR, INC.
3
QS7203, QS7204
First Load/ Retransmit (
FL
/
RT
)
This is a dual-purpose input. In the depth-expansion mode, this pin indicates the first FIFO device that will be
loaded or read from after a reset operation. In the standalone or width-expansion mode (when the expansion
input is grounded) this pin initiates the retransmit function.
Retransmit resets the read pointer to zero. The read and write signals must be HIGH before and after the rising
edge of the retransmit pulse. The retransmit feature is useful when the same data needs to be read again
without rewriting it into the FIFO. Pulsing the retransmit pin will cause the read pointer to be reset to zero, and
the previously read data can be read again. The flags will change according to the relative location of the
pointers after the retransmit pulse.
Expansion In (
XI
)
This is a dual-purpose pin. When it is grounded, it indicates that the FIFO is a standalone device. When it is
not grounded, it indicates that the FIFO is in the depth-expansion mode. In the depth-expansion mode, this
pin is connected to the
XO
pin of the previous device.
DATA OUTPUTS
Data Outputs Q8-Q0
The 9-bit data output bus Q8-Q0 receives the read data from the FIFO. It is active whenever the read signal
is LOW. It is in a high impedance state when the read signal is HIGH. It is also in high impedance when the
FIFO Empty flag is active (i.e., when the FIFO is empty).
CONTROL OUTPUTS
Full Flag (
FF
)
The Full flag indicates that the FIFO is full. The Full flag is asserted when there is only one empty location in
the FIFO and a falling edge of the write signal initiates the last write operation. The rising edge of the read signal
de-asserts the flag, as at least one location has become available.
Empty Flag (
EF
)
The Empty flag indicates the FIFO is empty. It is asserted when there is only one word in the FIFO, and a falling
edge of the read signal initiates the last read operation. The rising edge of the write signal de-asserts the flag,
as one word is now present in the FIFO.
Expansion Out/Half-Full Flag (
XO
/
HF
)
This is a dual-purpose flag. In the single-device mode, the expansion in (
XI
) is grounded and the Half-Full flag
output is present on this pin. Whenever the FIFO is more than half-full, the flag remains asserted . When the
FIFO is exactly half-full, the next falling edge of the write signal asserts the flag. The rising edge of read that
causes the FIFO to be half-full will de-assert the Half-Full flag. It will remain asserted until the FIFO is half-
full or less than half-full. The name given to the flag is half-full, but it is asserted on the one plus the half-full
condition.
In the depth-expansion mode, the expansion out (
XO
) is connected to the expansion in (
XI
) of the next device.
This causes the next device to perform write or read operations.
4
QUALITY SEMICONDUCTOR, INC.
MDSF-00002-04
APRIL 28, 1995
QS7203, QS7204
FUNCTION TABLES
RESET AND RETRANSMIT FUNCTION TABLE
Mode
Reset
Retransmit
Read/Write
RS
L
H
H
INPUTS
FL
/
RT
X
L
H
XI
L
L
L
INTERNAL STATUS
Read Pointer
Write Pointer
Location Zero
Location Zero
Increment
(1)
Location Zero
Unchanged
Increment
(2)
EF
L
(3)
(4)
OUTPUTS
1
HF
H
(3)
(4)
FF
H
(3)
(4)
2
Notes:
1. The read pointer will increment if the FIFO is not empty.
2. The write flag will increment if the FIFO is not full.
3. The flags will change after the retransmit operation and will correspond to the read pointer
being at location zero.
4. The flags will reflect the relative locations of the read and write pointers.
RESET AND FIRST-LOAD FUNCTION TABLE
Mode
Reset
Retransmit
Read/Write
RS
L
L
H
INPUTS
FL
/
RT
L
H
(2)
XI
(1)
(1)
(1)
INTERNAL STATUS
Read Pointer
Write Pointer
Location Zero
Location Zero
Increment
(1)
Location Zero
Location Zero
Increment
(2)
EF
L
(3)
(4)
OUTPUTS
FF
H
(3)
(4)
HF
H
(3)
(4)
Notes:
1. The expansion in (
XI
) is connected to the expansion out (
XO
) of the previous device.
2. The device with
FL
tied LOW will receive the first N writes and first N reads, where N is the FIFO size. On the Nth write,
the
XO
pulse is sent to the next device to indicate that it will receive the (N+1)th write. Similarly, on the Nth read, another
XO
pulse is sent to the next device to indicate that it will output the (N+1)th read.
3. The read and write pointers will be activated according to whether the FIFO received an
XO
pulse, or whether they were
the first device in the daisy chain. The flags will reflect the empty or full conditions for the individual FIFOs. To create
the composite Full and Empty flags, an OR-ing of the individual flags is required.
4. The flags will reflect the relative locations of the read and write pointers.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground .................................................. –0.5 to +7.0V
DC Output Voltage V
OUT
............................................ –0.5 to Vcc + 0.5V
DC Input Voltage V
IN
.................................................. –0.5 to Vcc + 0.5V
AC Input Voltage (Pulse Width
≤
20 ns) ......................................... –3.0V
DC Input Diode Current with V
IN
< 0 ........................................... –20 mA
DC Output Current with V
IN
> V
CC
................................................. 20 mA
DC Output Diode Current with V
OUT
< 0 ...................................... –50 mA
DC Output Current with V
OUT
> V
CC
.............................................. 50 mA
DC Output Current Max Sink Current/Pin ................................... +70 mA
DC Output Current Max Source Current/Pin ............................... –30 mA
Total DC Ground Current ....................................... (NxI
OL
+ Mx∆I
CC
) mA
Total DC V
CC
Power Supply Current ...................... (NxI
OH
+ Mx∆I
CC
) mA
(N = Number of Outputs, M = Number of Inputs)
T
STG
StorageTemperature ............................................ –65°C to +150°C
Note:
Stresses greater than
those listed under ABSOLUTE
MAXIMUM RATINGS may
cause permanent damage to
this device, resulting in func-
tional- or reliability-type failures.
MDSF-00002-04
APRIL 28, 1995
QUALITY SEMICONDUCTOR, INC.
5
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