S29WS064J0PBAI01 datasheet, PDF

Datasheet> All Categories > storage> storage> S29WS064J0PBAI01

S29WS064J0PBAI01: DescriptionFlash, 4MX16, 55ns, PBGA80, 7 X 9 MM, FBGA-80; Categorystorage storage; File Size2MB，110 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

Download Datasheet Parametric View All

S29WS064J0PBAI01 Overview

Flash, 4MX16, 55ns, PBGA80, 7 X 9 MM, FBGA-80

S29WS064J0PBAI01 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	VFBGA, BGA80,8X10,32
Contacts	80
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	55 ns
Other features	SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
startup block	BOTTOM/TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B80
JESD-609 code	e3
length	9 mm
memory density	67108864 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	16,126
Number of terminals	80
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA80,8X10,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	4K,32K
Maximum standby current	0.00005 A
Maximum slew rate	0.054 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
switch bit	YES
type	NOR TYPE
width	7 mm
Base Number Matches	1

Preview

Download Datasheet

View All

S29WS128J/064J

128/64 Megabit (8/4 M x 16-Bit)

CMOS 1.8 Volt-only Simultaneous Read/Write,

Burst Mode Flash Memory

Distinctive Characteristics

Architectural Advantages

Single 1.8 volt read, program and erase (1.65 to

1.95 volt)

Manufactured on 0.11 µm process technology

VersatileIO™ (V

) Feature

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V

— 1.8V compatible I/O signals (1.65-1.95 V)

— 1.5V compatible I/O signals (1.35-1.70 V)

Simultaneous Read/Write operation

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/

16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb

Programable Burst Interface

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with wrap-around

— Continuous Sequential Burst

SecSi™ (Secured Silicon) Sector region

— 128 words accessible through a command sequence,

64words for the Factory SecSi™ Sector and 64words

for the Customer SecSi™ Sector.

Sector Architecture

4 Kword x 16 boot sectors, eight at the top of the address

range, and eight at the bottom of the address range

—

WS128J:

4 Kword X 16, 32 Kword x 254 sectors

Bank A : 4 Kword x 8, 32 Kword x 31 sectors

Bank B : 32 Kword x 96 sectors

Bank C : 32 Kword x 96 sectors

Bank D : 4 Kword x 8, 32 Kword x 31 sectors

—

WS064J:

4 Kword x 16, 32 Kword x 126 sectors.

Bank A : 4 Kword x 8, 32 Kword x 15 sectors

Bank B : 32 Kword x 48 sectors

Bank C : 32 Kword x 48 sectors

Bank D : 4 Kword x 8, 32 Kword x 15 sectors

WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,

WS064J : 80-ball (7 mm x 9 mm) FBGA package

Cyclling Endurance : 1,000,000 cycles per sector

typical

Data retention : 20-years typical

ADVANCE

INFORMATION

Performance Charcteristics

Read access times at 104/80/66 MHz

— Burst access times of 7.0/9.1/11.2 ns @ 30 pF at

industrial temperature range

— Synchronous latency of 45.5/46/56 ns (at 30 pF)

— Asynchronous random access times of 45/45/55 ns

(at 30 pF)

Power dissipation (typical values, C

= 30 pF)

— Burst Mode Read: 10 mA @ 80Mhz

— Simultaneous Operation: 25 mA @ 80Mhz

— Program/Erase: 15 mA

— Standby mode: 0.2 µA

Hardware Features

Handshaking feature available

— Provides host system with minimum possible latency

by monitoring RDY

Hardware reset input (RESET#)

— Hardware method to reset the device for reading

array data

WP# input

— Write protect (WP#) function allows protection of

four outermost boot sectors, regardless of sector

protect status

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

— Sectors can be locked and unlocked in-system at V

level

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

ACC input: Acceleration function reduces

programming time; all sectors locked when ACC =

CMOS compatible inputs, CMOS compatible outputs

Low V

write inhibit

Publication Number

WS128J/064J_00

Revision

Amendment

Issue Date

October 6, 2004

This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in

this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.

A D V A N C E

I N F O R M A T I O N

General Description

The S29WS128J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write,

Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits

each. This device uses a single V

of 1.65 to 1.95 V to read, program, and erase the

memory array. A 12.0-volt V

on ACC may be used for faster program performance if

desired. The device can also be programmed in standard EPROM programmers.

At 104 MHz, the device provides a burst access of 7.0 ns at 30 pF with a latency of 45.5

ns at 30 pF. At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a la-

tency of 46 ns at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF

with a latency of 56 ns at 30 pF. The device operates within the industrial temperature

range of -40°C to +85°C and the wireless temperature range of -25°C to +85°C. The de-

vice is offered in Various FBGA packages.

The Simultaneous Read/Write architecture provides

simultaneous operation

by divid-

ing the memory space into four banks. The device can improve overall system perfor-

mance by allowing a host system to program or erase in one bank, then immediately and

simultaneously read from another bank, with zero latency. This releases the system from

waiting for the completion of program or erase operations.

The device is divided as shown in the following table:

Quantity

Bank

128Mb

64 Mb

Size

4 Kwords

32 Kwords

4 Kwords

The VersatileIO™ (V

) control allows the host system to set the voltage levels that the

device generates at its data outputs and the voltages tolerated at its data inputs to the

same voltage level that is asserted on the V

pin.

The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-

put Enable (OE#) to control asynchronous read and write operations. For burst opera-

t i on s , t h e d e v i c e a dd i t i o n a l l y r e q u i r e s Re a d y ( R D Y ) , a n d C l o c k ( C L K ) . T h i s

implementation allows easy interface with minimal glue logic to a wide range of micropro-

cessors/microcontrollers for high performance read operations.

The burst read mode feature gives system designers flexibility in the interface to the de-

vice. The user can preset the burst length and wrap through the same memory space, or

read the flash array in continuous mode.

The clock polarity feature provides system designers a choice of active clock edges, either

rising or falling. The active clock edge initiates burst accesses and determines when data

will be output.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-

supply Flash standard.

Commands are written to the command register using standard

microprocessor write timing. Register contents serve as inputs to an internal state-ma-

chine that controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out

of the device is similar to reading from other Flash or EPROM devices.

The

Erase Suspend/Erase Resume

feature enables the user to put erase or program

on hold for any period of time to read data from, or program data to, any sector that is

not selected for erasure. True background erase can thus be achieved. If a read is needed

from the SecSi™ Sector area (One Time Program area) after an erase suspend, then the

user must use the proper command sequence to enter and exit this region. Program sus-

pend is also offered.

The

hardware RESET# pin

terminates any operation in progress and resets the internal

state machine to reading array data. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the device, enabling the system microproces-

sor to read boot-up firmware from the Flash memory device.

October 6, 2004

WS128J/064J_00_A1_E

S29WS128J/064J

A D V A N C E

I N F O R M A T I O N

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block Diagram of Simultaneous Operation Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9

Special Handling Instructions for FBGA Package .......................... 9

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 10

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 16

Table 1. Device Bus Operations ..........................................16

Table 8. CFI Query Identification String .............................. 36

System Interface String ..................................................... 37

Table 10. Device Geometry Definition........................................ 37

Table 11. Primary Vendor-Specific Extended Query ............... 38

Table 12. WS128J Sector Address Table .............................. 39

Table 13. WS064J Sector Address Table .............................. 47

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 53

Reading Array Data ..............................................................................53

Set Configuration Register Command Sequence ........................53

Figure 3. Synchronous/Asynchronous State Diagram ............. 54

Read Mode Setting ............................................................................... 54

Programmable Wait State Configuration ...................................... 54

Table 14. Programmable Wait State Settings ....................... 55

VersatileIO™ (V

) Control ................................................................ 16

Requirements for Asynchronous ReadOperation (Non-Burst) ..

...................................................................................................................... 16

Requirements for Synchronous (Burst) Read Operation ......... 17

8-, 16-, and 32-Word Linear Burst with Wrap Around .............18

Table 2. Burst Address Groups ............................................18

Standard wait-state Handshaking Option ..................................... 55

Table 15. Wait States for Standard wait-state Handshaking .. 55

Read Mode Configuration .................................................................. 55

Table 16. Read Mode Settings ............................................ 56

Configuration Register ......................................................................... 18

Handshaking ............................................................................................18

Simultaneous Read/Write Operations with Zero Latency ....... 19

Writing Commands/Command Sequences ................................... 19

Accelerated Program Operation ...................................................... 19

Autoselect Mode ..................................................................................20

Table 3. Autoselect Codes (High Voltage Method) .................21

Burst Active Clock Edge Configuration ......................................... 56

RDY Configuration .............................................................................. 56

Configuration Register .........................................................................56

Table 17. Configuration Register ........................................ 57

Reset Command ................................................................................... 57

Autoselect Command Sequence ...................................................... 57

Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence 58

Program Command Sequence .......................................................... 59

Unlock Bypass Command Sequence ............................................... 59

Figure 4. Program Operation .............................................. 60

Sector/Sector Block Protection and Unprotection .................... 21

Table 4.

S29WS128J Boot Sector/Sector Block

Addresses for Pro-

tection/Unprotection ..........................................................21

Table 5.

S29WS064J Boot Sector/Sector Block

Addresses for Pro-

tection/Unprotection ..........................................................23

Chip Erase Command Sequence ......................................................60

Sector Erase Command Sequence ................................................... 61

Erase Suspend/Erase Resume Commands .................................... 62

Figure 5. Erase Operation .................................................. 63

Sector Protection ................................................................................. 25

Persistent Sector Protection ............................................................. 25

Persistent Protection Bit (PPB) ........................................................ 26

Persistent Protection Bit Lock (PPB Lock) ................................... 26

Dynamic Protection Bit (DYB) ......................................................... 26

Table 6.

Sector Protection Schemes .....................................27

Persistent Sector Protection Mode Locking Bit .......................... 28

Password Protection Mode ...............................................................28

Password and Password Mode Locking Bit .................................. 28

64-bit Password ..................................................................................... 29

Persistent Protection Bit Lock ......................................................... 29

Standby Mode ........................................................................................ 29

Automatic Sleep Mode ........................................................................ 30

RESET#: Hardware Reset Input ....................................................... 30

Output Disable Mode ........................................................................... 31

Figure 1. Temporary Sector Unprotect Operation................... 31

Figure 2. In-System Sector Protection/Sector Unprotection Algo-

rithms ............................................................................. 32

Password Program Command .......................................................... 63

Password Verify Command ............................................................... 63

Password Protection Mode Locking Bit Program Command . 64

Persistent Sector Protection Mode Locking Bit Program Com-

mand ......................................................................................................... 64

SecSi™ Sector Protection Bit Program Command ..................... 64

PPB Lock Bit Set Command .............................................................. 64

DPB Write/Erase/Status Command ................................................ 65

Password Unlock Command ............................................................. 65

PPB Program Command ..................................................................... 65

All PPB Erase Command .................................................................... 66

PPB Status Command .......................................................................... 66

PPB Lock Bit Status Command ........................................................ 66

Command Definitions ......................................................................... 67

Table 18. Command Definitions ........................................ 67

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 70

DQ7: Data# Polling .............................................................................. 70

Figure 6. Data# Polling Algorithm ....................................... 71

SecSi™ (Secured Silicon) Sector Flash Memory Region .............33

Table 7. SecSi™ Sector Addresses ......................................33

SecSi™ Sector Protection Bit ............................................................. 34

Hardware Data Protection ................................................................ 34

Write Protect (WP#) .......................................................................... 34

Low V

Write Inhibit ........................................................................35

Write Pulse “Glitch” Protection .......................................................35

Logical Inhibit ..........................................................................................35

Power-Up Write Inhibit ......................................................................35

Common Flash Memory Interface (CFI) . . . . . . . 36

RDY: Ready .............................................................................................72

DQ6: Toggle Bit I .................................................................................. 72

Figure 7. Toggle Bit Algorithm ............................................ 73

DQ2: Toggle Bit II .................................................................................73

Table 19. DQ6 and DQ2 Indications .................................... 74

Reading Toggle Bits DQ6/DQ2 ........................................................ 74

DQ5: Exceeded Timing Limits .......................................................... 75

DQ3: Sector Erase Timer .................................................................. 75

Table 20. Write Operation Status ....................................... 76

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 77

October 6, 2004

WS128J/064J_00_A1_E

S29WS128J/064J

Recommended Resources

Differential bridge amplifier circuit diagram

DC operated circuit breaker tripping and closing circuit

CMOS-Light Emitting Diode LED Interface

Simple TV signal generator circuit

Temperature adjustment interface circuit using silicon temperature sensor KTYlo

Computer motherboard circuit diagram 440BX_04

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components