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KESRX02
260 to 470MHz ASK Receiver with Power Down
DS4968 - 1.2 May 1998
The KESRX02 is a single chip ASK (Amplitude Shift Key)
receiver integrated circuit. It is designed to operate in a variety
of low power radio applications including keyless entry, general
domestic and industrial remote control, RF tagging and local
paging systems.
The receiver offers an exceptionally high level of integration
and performance to meet the requirements of regulatory
authorities world wide.
Functionally, the device works in the same way as the
KESRX01 but with the added feature of a two-stage power
down to enable receiver systems to be implemented with less
than 1mA supply current, and a wide IF bandwidth and drive
stage to interface with an external ceramic IF bandpass filter at
intermediate frequencies from 200kHz to 15 MHz.
IFDC1
IFIN
IFDC2
V
CC
IFOUT
V
CC
RF
MIXIP
RFOP
V
EE
RF
RFIN
DREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
IFFLT1
IFFLT2
PD
XTAL1
XTAL2
DF0
DF1
DF2
DSIN
VCO1
VCO2
V
EE
LF
DSN
KESRX02
22
21
20
19
18
17
16
15
FEATURES
I
2103dBm
Sensitivity (Typical)
AGC
PEAK
DATOP
I
AGC around LNA and Mixer
I
Low Supply Voltage: 4·5V to 5·5V
I
Low Supply Current: 3·7mA (Typical)
I
Two-Stage Power Down for Very Low Current
QPA28
Fig. 1 Pin connections - top view
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Signal
IFDC1
IFIN
IFDC2
V
CC
IFOUT
V
CC
RF
MIXIP
RFOP
V
EE
RF
RFIN
DREF
AGC
PEAK
DATOP
DSN
LF
V
EE
VCO2
VCO1
DSIN
DF2
DF1
DF0
XTAL2
XTAL1
PD
IFFLT2
IFFLT1
Function
Log amp DC stability capacitor
Log amp input
Log amp DC stability capacitor
Positive supply
IF output to external IF filter
Positive supply for RF circuits
Mixer input
Output from LNA
Negative supply for RF circuits
Input to LNA
Data reference voltage (DSIN clamp)
RF AGC time constant
Data signal peak detect
Sliced data output
Data slice level
PLL loop filter
Negative supply
Voltage controlled oscillator
Voltage controlled oscillator
Signal input to data slicer
Op amp output for data filter
Op amp input for data filter
RSSI output and data filter
Crystal oscillator
Crystal oscillator
Power down
Noise reducing IF filter
Noise reducing IF filter
Applications
I
Integrated VCO and Data Filters
I
Interface for Ceramic IF Filters up to 15MHz
I
Suitable for Unlicensed Applications Compliant
with FCC and ETSI Requirements
I
ESD Protected (Normal ESD Handling should be
observed)
I
Muted Data Output
APPLICATIONS
I
Remote Keyless Entry
I
Security, Tagging
I
Remote Controlled equipment
ORDERING INFORMATION
KESRX02/IG/QP1S
Antistatic tubes
KESRX02/IG/QP1T
Tape and reel
ELECTROSTATIC PROTECTION
Standard ESD protection has been applied to meet the 2kV
Human Body requirement. All pins meet the 2kV requirement
except pins 18 and 19, which are limited to 1kV, and pins 8 and
10, which are limited to 500V.
ABSOLUTE MAXIMUM RATINGS
Supply voltage V
CC
Storage temperature, T
STG
Junction temperature, T
J
RF input power
20·5
to17V
255°C
to
1150°C
255°C
to
1150°C
120dBm
from 50Ω source
Table 1 Pin descriptions
KESRX02
DESCRIPTION
The single-conversion superheterodyne receiver approach is
now considered the way forward for ISM band type applications
because of lower cost, superior selectivity, lower radiation and
flexibility over other techniques. For power-conscious hand held
applications, KESRX02 provides improved performance and
flexibility with a power down feature which allows faster switch-on
times of less than 1ms for use in a pulsed power saving mode.
Despite the KESRX02 being a relatively simple receiver, the
flexibility of using an external IF filter allows the designer to choose
both the selectivity and the IF in order to optimise performance for
a wide range of applications and locations world wide.
Fig. 2 is a simplified system block diagram for the device with
an external ceramic IF filter.
RF
MIXER
RF
434MHz
LNA
EXTERNAL
IF FILTER
PEAK
DETECTOR
DATA
FILTER
SLICER
SLICED DATA
DATA
SLICE
LEVEL
LOCAL
OSCILLATOR
(VCO)
Fig. 2 KESRX02 system block diagram
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed by either production test or design over the following range of operating conditions:
T
AMB
=
240°C
to
185°C,
V
CC
= 4·5V to 5·5V
DC Characteristics
Value
Characteristic
Supply Current
Receive mode
Power down 1
Power down 2
Symbol
Min.
Typ.
Max.
Units
Conditions
I
CC
I
CC1
I
CC2
3·7
0·33
33
4·5
0·5
50
mA
mA
µA
All. PD = high, RF input
,250dBm
All. PD = V
CC
/2 or high impedance source
All. PD = low
AC Characteristics
Value
Characteristic
Input frequency range
LNA parallel input resistance
LNA parallel input capacitance
LNA noise matching impedance
Sensitivity
Max RF input
Data rate
LNA noise figure
1dB compression point
Intermediate frequency
VCO frequency
Conducted emissions
Data output voltage high
Data output voltage low
LNA parallel output R
LNA parallel output C
Symbol
f
S
R
IN
C
IN
V
IN(MIN)
V
IN(MAX)
NF
0·2
f
LO
V
OH
V
OL
V
CC
20·7
0·7
8·8
1·7
Min.
260
0·8
1·6
Typ.
Max.
470
1·2
2·0
Units
MHz
kΩ
pF
kΩ//nH
µVrms
Vrms
kB/s
dB
dBm
MHz
MHz
µVrms
V
V
kΩ
pF
Conditions
All
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
25°C, 1kB/s data rate (note 1)
All (note 2)
At reduced sensitivity (note 5)
25°C, f
S
= 434MHz, matched 50Ω environment
25°C, f
S
= 434MHz
All. (note 3)
All
265dBm
(note 4)
I
OH
= 10µA
I
OL
=
210µA
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
cont…
1·0
1·8
1·0//4·6
1·5
0·5
120
4·5
220
15
485
125
2
KESRX02
AC Characteristics (continued)
Value
Characteristic
Mixer parallel input R
Mixer parallel input C
IF1 output impedance
IF2 input impedance
Receiver Gains
LNA
Mixer conversion gain
IF gain of log amp
Symbol
Min.
1·3
1·4
240
3·2
A
LNA
A
MIX
A
LOG
Typ.
1·6
1·8
300
4·0
13
9
80
Max.
2·0
2·2
360
4·8
Units
kΩ
pF
Ω
kΩ
dB
dB
dB
Conditions
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
25°C, f
S
= 434MHz
LNA matched to mixer input impedance
Measured at input to ceramic filter.
Includes 6dB matching loss.
All.
NOTES
1. Sensitivity is defined as the average signal level, measured at the input, necessary to achieve a bit error rate (BER) of 0·01, where
the input signal is a return-to-zero pulse with an average duty cycle of 50% and 1kB/s data rate. Equivalent to
2103dBm
for 50Ω
input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz bandwidth and a data
filter bandwidth of 5kHz. This equates closely to a measurement of tangential sensitivity.
2. Peak RF input level on RFIN pin for overload of the demodulator with AGC operating. Equivalent to
17dBm
for 50Ωinput impedance.
3. Actual IF frequency determined by choice of crystal and external ceramic filter.
4. Local oscillator VCO power fed back into 50Ω source at RF input, measured with RF input matching network (see Fig. 6).
5. Data rate is given assuming intermediate frequency and data filters are optimally set.
FUNCTIONAL OPERATION
Power Down
The PD pin is a tristate input, providing a 2-stage power down
for the receiver. The receiver is fully operational when PD is high
and is powered down when PD is taken to ground (see Table 2).
PD (pin 26)
Low (0V)
V
CC
/2
High (V
CC
)
Status
Full PD, with V
CC
applied to chip
PD, reference crystal oscillator ‘ON’
Receive, fully operational
balanced mixer through an external impedance matching
circuit, RFOP to MIXIP.
The AGC circuit monitors the mixer signal output level.
Control is fed back, applying AGC to the LNA to prevent
overload in the Mixer and the generation of unwanted distortion
products. This also has the effect of reducing the RSSI
characteristic slope and extending its range of operation by
more than 20dB at high signal levels (see Fig. 5).
The AGC circuit comes into operation at input signal levels
greater than about
235dBm
and reduces the LNA gain by
6dB at an input signal level of about
225dBm.
Since the AGC
operates on the mixer output signal level, the exact point at
which the AGC comes into operation depends on the
conversion gain between the antenna feed and the mixer
output.
Table 2 PD functions
PD Low
None of the receiver circuits are functional. I
CC
is reduced to
its lowest level (,50µA with V
CC
applied). A longer settling time
is required to restore full performance after switching to receive
mode (PD high).
PD = V
CC
/2 or high impedance source (CMOS tristate)
A non-receiving state with a few critical circuits running,
including the crystal oscillator. Current consumption I
CC
is
reduced to about 330µA. When switching to the receive state,
data can start to be recovered within 1ms of PD going high for
signals close to maximum sensitivity.
PD high
The receiver is fully functional and ready to receive data
IF Interface
There is no on-chip IF filter on the KESRX02 in order to
provide the flexibility for the system designer to choose a low
or high IF up to 15MHz. Typically, a 10·7 MHz ceramic filter
will be connected between IFOUT and IFIN together with an
input RF SAW filter to give improved image channel rejection.
The choice of bandwidth for the 10·7MHz ceramic filter
depends on frequency tolerancing of the transmitter, receiver,
data rate and component cost.
The IF filter drive, IFOUT, is a voltage drive with a 300Ω
series resistance. This allows impedance matching to the
ceramic filter to be set by an external series resistor. However,
if a 10·7MHz ceramic filter with a typical input impedance of
300Ω is used then no external resistor is required at IFOUT.
The input to the log amp, IFIN, is a high impedance with an
internal 4kΩ shunt resistor. Impedance matching between
the ceramic filter output and IFIN is achieved with an external
shunt resistor (R9 on Fig. 6) between IFIN and IFDC1.
RF Down-Converter
An internal Low Noise Amplifier (LNA) is designed to
interface to an input SAW filter with a maximum insertion loss
of 3dB.
The LNA gain is approximately 13 dB at 460MHz when
matched to the mixer input, while the LNA noise figure is
typically 4·5dB when matched in a 50Ω environment input and
output.
The internal LNA is conditionally stable and feeds a double-
3
KESRX02
Phase Locked Loop VCO
The local oscillator is a VCO locked to a crystal reference by
a phase locked loop (PLL). The VCO gain is nominally 40MHz/V
depending on the external varactor diode used. The VCO
frequency is divided down by a fixed
464
prescaler and input to
the phase/frequency detector, where the reference frequency is
provided by the crystal oscillator. The phase detector output
current into the PLL loop filter is
630µA
and the maximum loop
filter bandwidth is 50kHz.
Conducted VCO signal signals capable of being radiated
from the antenna of the complete receiver are suppressed to a
level of
,265dBm
into 50Ω.
slow decay time, the gain of the stage remains constant during
the data burst. This means that the change in output for a given
extinction ratio also remains constant at approximately 16mV/dB
up to a peak input signal level of 0dB. This requires the decay
time constant to exceed the transmitted bit period and no long
period of zero signal power has been transmitted.
Baseband
The RSSI output will contain wideband demodulated noise
and signals that are within the RF and IF filter pass bands. An
additional data low pass filter is therefore used to improve overall
sensitivity.
KESRX02 has an integrated second order Sallen and Key
data filter whose response characteristic is set by R10, R11, C5
and C6. Fig. 4 shows the connections and calculation for the
23dB cut-off frequency and filter type, normally Bessel.
The cut-off frequency is determined from the data rate and the
level of pulse distortion that can be tolerated. It is usually set at
3 times the maximum data frequency.
The output from this filter, DF2, is AC-coupled into the data
slicer, where the signal is first DC restored on the negative peaks,
then a peak detector recovers the signal amplitude on C22 (Fig.
6). The DC restored signal is input to the inverting input of the
data slice comparator, DSIN, with the slice level applied to the
non-inverting input, DSN.
The data slice level is referenced to peak signal level and is
set by the potential divider R6 and R8 (Fig. 6) between the PEAK
and DREF pins. DREF is the reference voltage to which the data
signal is DC restored.
This method can apply a squelch when there are very low
level noisy signals by adding a resistor from DSN to ground. This
resistor provides an offset to the slice voltage.
The data slicer output, DATOP, is CMOS compatible but is
only capable of driving capacitive loads
,20pF,
depending on
the data rate. Its output is the inverse of the input at DSIN. The
output drive current is nominally
615µA,
so that in a system
using high data rates or higher capacitive loads (for example,
long track lengths), it may be necessary to incorporate a buffer
to ensure the required edge speeds to the following logic. The
data slicer has built-in hysteresis to reduce edge chatter.
The sense of the squelch on the data output is low when no
signal is present. This could be confusing as a low output during
a data burst also corresponds to the ‘on’ period, that is, the mark
of the RFOOK signal. However, it is the first pulse of the data
signal that causes the peak detector capacitor to charge and in
doing so sets the appropriate slice level. As a consequence, the
first pulse of the data transmission may be lost as the receiver
adapts to the incoming signal level.
IF Amp/RSSI Detector
This is a logarithmic amplifier with a gain of
.80dB
and an
RSSI output used as the detector. The 3dB bandwidth of the IF
log amplifier is typically 20MHz to allow high IFs to be used.
Normally, a wide IF bandwidth would limit the overall sensitivity
of the receiver due to the amplified wideband noise generated in
the first IF stage.
The RSSI generator is not frequency selective so that any
wideband noise introduced after the ceramic filter will be detected
as signal. A simple LC filter is therefore connected part-way
down the log amp to reduce the noise power from the earlier
stages. Typically, this filter only needs to be a fixed component
LC filter between IFFLT1 and IFFLT2 (pins 28 and 27) with a
1MHz bandwidth (Q
≈
10). There is an internal 20kΩ damping
resistance across these pins which will determine the Q and the
values of L5 and C7, as follows:
L5 = 20000
2pf
IF
Q
C7 =
Q
2pf
IF
320000
A ceramic resonator or filter is not a suitable component here
as a low impedance DC path must be maintained to remove DC
voltage offsets in the high gain log amplifier. Further improvements
in sensitivity can be gained by using a narrow band IF ceramic
filter and a narrower noise reduction filter.
For a low IF receiver,,1MHz, a low pass filter can be used for
both the IF and noise reduction filters but such a receiver would
have virtually no image rejection capability.
The RSSI output transfer characteristic at DF0 (pin 23) has a
slope of approximately 16mV/dB. A typical transfer characteristic
from LNA input to RSSI output is shown in Fig. 5, measured with
a constant RF input signal. This shows the effect of the AGC in
extending the range of the detector to a
110dBm
input signal and
includes the effect of the AGC circuit adapting to this signal level.
Because the RF amplifier AGC has a fast attack time and a
RFOP
8
MIXIP
7
IFOUT
5
IFIN
2
IFFLT1 IFFLT2 IFDC2 IFDC1
28
27
3
1
DF0 DF1
23
22
DF2 DSIN
21
20
13
PEAK
PEAK DET
V
CC
RF
AGC
6
12
DATA FILTER
AMPLIFIER
AGC
LOG AMP
−
+
14
DATOP
4
64
RFIN
10
PHASE/
FREQUENCY
DETECTOR
REFERENCE
CRYSTAL
OSCILLATOR
DATA
SLICER
15
1
DSN
DREF
LNA
VCO
9
18
19
26
4
17
16
24
25
V
EE
RF
VCO2
VCO1
PD
V
CC
V
EE
LF
XTAL2
XTAL1
Fig. 3 KESRX02 block diagram
4
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