Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
DESCRIPTION
The Philips 83C754/87C754 offers many of the advantages of the
80C51 architecture in a small package and at low cost.
PIN CONFIGURATION
RxD/T0/P3.4/D4
1
2
3
4
5
6
7
8
9
10
11
CERAMIC
DUAL
IN-LINE
PACKAGE
AND
PLASTIC
SHRINK
SMALL
OUTLINE
PACKAGE
28 P3.3/D3
27 P3.2/D2
26 P3.1/D1
25 P3.0/D0
24 INT0/P1.0/A0/A8
23 CEX/P1.1/A1/A9
22 V
CC
21 V
PP
/P1.2
20 XYDAC/A7
19 ZDAC/ASEL
18 XYSOURCE/A6
17 XYDACBIAS/PGM
16 VREG
15 DECOUPLE
The 8XC754 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up senitivity.
The 8XC754 contains a 4k
×
8 ROM (83C754) EPROM (87C754), a
single module PCA, a 256
×
8 RAM, 11 I/O lines, two 16-bit
counter/timers, a two-priority level interrupt structure, a full duplex
serial channel, an on-chip oscillator, and an 8-bit D/A converter.
The EPROM version of this device, the 87C754, is available in
plastic one-time programmable (OTP) packages. Once the array
has been programmed, it ifs functionally equivalent to the masked
ROM 83C754. Thus, unless explicitly stated otherwise, all
references made to the 87C754 apply equally to the 83C754.
The 8XC754 supports two power reduction modes of operation
referred to as the idle mode and the power-down mode.
TxD/T1/P3.5/D5
ECI/P3.6/D6
INT1/P3.7/D7
RST
X2
X1
V
SS
ZIN/A2/A10
YIN/A3/A11
XIN/A4
XYZRAMP/A5 12
AV
SS
13
FEATURES
packages
AV
CC
14
•
Available in erasable quartz lid or One-Time Programmable plastic
•
80C51-based architecture
•
Small package sizes – 28-pin SSOP
•
Wide oscillator frequency range
•
Power control modes:
–
Idle mode
–
Power-down mode
SU00665D
•
4k
×
8 ROM (83C754)
EPROM (87C754)
•
256
×
8 RAM
•
Two 16-bit auto reloadable counter/timers
•
Single module PCA counter/timer
•
Full duplex serial channel
•
Boolean processor
•
CMOS and TTL compatible
PART NUMBER SELECTION
ROM
P83C754EBD DB
EPROM
1
P87C754EBD DB
OTP
TEMPERATURE RANGE
°C
AND PACKAGE
0 to +70, 28-pin Shrink Small Outline Package
FREQUENCY
3.5 to 16MHz
DRAWING
NUMBER
SOT341-1
NOTE:
1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM.
1998 Apr 23
2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
PIN DESCRIPTION
MNEMONIC
V
SS
V
CC
P1.0–P1.2
DIP
PIN NO.
8
22
21, 23, 24
TYPE
I
I
I/O
Circuit Ground Potential.
Supply voltage during normal, idle, and power-down operation.
Port 1:
Port 1 is a 3-bit bidirectional I/O port with internal pull-ups on P1.0 and P1.1. Port 1 pins that
have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: I
IL
).
Port 1 also serves the special function features listed below (Note: P1.0 does
not
have the strong
pullup that is on for 2 oscillator periods.):
INT0 (P1.0):
External interrupt 0.
CEX (P1.1):
PCA clock output.
V
PP
(P1.2):
Programming voltage input (open drain).
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 3 also functions as the data input for the EPROM memory location to be
programmed (or verified). (Note: P3.5 does
not
have the strong pullup that is on for 2 oscillator
periods.)
Port 3 also serves the special function as listed below:
ECI (P3.6):
External PCA clock input.
RxD/T0 (P3.4):
Serial port receiver data input.
Timer 0 external clock input.
INT1:
External interrupt 1.
TxD/T1 (P3.5):
Serial port transmitter data.
Timer 1 external clock input.
Reset:
A high on this pin for two machine cycles while the oscillator is running resets the device. After
the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the
programming state allowing programming address, data and V
PP
to be applied for programming or
verification purposes. The RESET serial sequence must be synchronized with the X1 input. (Note: The
83/87C754 does not have an internal reset resistor.)
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
Crystal 2:
Output from the inverting oscillator amplifier.
Analog supply voltage and reference input.
Analog supply and reference ground.
ZIN:
Input to analog multiplexer.
YIN:
Input to analog multiplexer.
XIN:
Input to analog multiplexer.
XYZRAMP:
Provides a low impedance pulldown to V
SS
under S/W control.
Decouple:
Output from regulated supply for connection of decoupling capacitors.
VREG:
Provides regulated analog supply output.
XYDACBIAS:
Provides source voltage for bias of external circuitry.
–
Input which specifies verify mode (output enable) or the program mode.
/PGM = 1 output enabled (verify mode).
/PGM = 0 program mode.
XYSOURCE
ZDAC
18
19
O
O
XYSOURCE:
Provides source voltage from regulated analog supply.
ZDAC:
Switchable outp from the internal DAC.
ASEL (P0.0) –
Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
XYDAC
20
O
XYDAC:
Non-switchable output from the internal DAC.
NOTE:
1. AV
SS
(reference ground) must be connected to 0V (ground). AV
CC
(reference input) cannot differ from V
CC
by more than
±0.2V,
and must be
in the range 4.5V to 5.5V.
1998 Apr 23
4
NAME AND FUNCTION
24
23
21
P3.0–P3.7
1–4,
25–28
I
O
I
I/O
3
1
4
2
RST
5
I
I
I
I
I
X1
7
I
X2
AV
CC 1
AV
SS 1
ZIN
YIN
XIN
XYZRAMP
DECOUPLE
VREG
XYDACBIAS
6
14
13
9
10
11
12
15
16
17
O
I
I
I
I
I
O
O
O
O
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
STANDARD SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
has not been read by the time reception of the second byte is
complete, one of the bytes will be lost.) The serial port receive and
transmit registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading
SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:
Mode 0:
Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/received (LSB first). The
baud rate is fixed at 1/12 the oscillator frequency.
Mode 1:
10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On Receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Mode 2:
11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On Transmit,
the 9th data bit (TB8 in SCON) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW)
could be moved into TB8. On Receive, the 9th data bit
goes into RB8 in Special Function Register SCON, while
the stop bit is ignored. The baud rate is programmable to
either 1/32 or 1/64 the oscillator frequency.
Mode 3:
11 its are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except baud
rate. the baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
IDLE MODE
The 8XC754 includes the 80C51 power-down and idle mode
features. In idle mode, the CPU puts itself to sleep while all of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset. Upon
powering-up the circuit, or exiting from idle mode, sufficient time
must be allowed for stabilization of the internal analog reference
voltages before a D/A conversion is started.
Special Function Registers
The special function registers (directly addressable only) contain all
of the 8XC754 registers except the program counter and the four
register banks. Most of the special function registers are used to
control the on-chip peripheral hardware. Other registers include
arithmetic registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Twelve of the SFRs are bit
addressable.
Data Pointer
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C754 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
Multiprocessor Communications
Modes 2 and 2 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 9 in a data byte. With SM2 = 1,
no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The addressed slave
will clear its SM2 bit and prepare to receive the data bytes that will
be coming. The slaves that were not being addressed leave their
SM2s set, and go on about their business, ignoring the coming data
bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Idle
Power-down
Port 1
Data
Data
Port 3
Data
Data
1998 Apr 23
5
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