CPU, SDRAM Output on Resistance: ............................. 15Ω
Logic inputs have 250K-ohm pull-up resistors
Block Diagram
REF
PLL Ref Freq
SSON#
SS%1
SS%0
Pin Configuration
[2, 3]
VDDCORE
REF
GND
X1
X2
SDRAM3
SDRAM2
VDDS
SDRAM1
SDRAM0
GND
VDDCORE
*SDEN
*SS%0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
USBCLKEN
GND
USBCLK
VDDU
CPU0
CPU1
VDDC
CPU2
CPU3
GND
SS%1*
SSON#^
FS1*
FS0*
X1
X2
XTAL
OSC
CPU0:3
SDRAM0:3
PLL 1
FS0
FS1
SDEN
USBCLKEN
PLL 2
USBCLK
Notes:
1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
2. Signals marked with [*] have internal pull-up resistors
3. Signal marked with[^] has internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07268 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 19, 2005
CY24242
Pin Definitions
Pin Name
CPU0:3
Pin
No.
24, 23, 21,
20
10, 9, 7, 6
15, 16
14, 18
26
Pin
Type
O
Pin Description
CPU Clock Outputs:
These four outputs run at a frequency set by FS0:1. The
width of the Spread Spectrum Modulation is enabled by pin SSON#, and
selected by pins SS%0:1.
SDRAM Outputs:
These four SDRAM clock outputs run synchronously to the
CPU clock. Modulation and frequency follow the CPU outputs.
Frequency Selection Inputs:
Selects CPU clock frequency as shown in
Table 1.
Modulation Width Selection Inputs:
These inputs select the width of the
Spread Spectrum feature when it is enabled by SSON#.
USB Output:
Timing signal running at 48.0080 MHz when a 14.31818-MHz
frequency is provided as the reference. (167 ppm accuracy to 48 MHz, the
output is equal to the reference times 57/17.)
CPU Spread Spectrum Enable Input:
When this pin is pulled LOW, outputs
CPU0:3 and SDRAM0:3 will have the Spread Spectrum Feature enabled.
USB Disable Input:
When this pin is pulled LOW, output USBCLK will be
disabled to a LOW state.
Reference Output:
This output will be equal in frequency to the reference
signal provided at X1/X2.
SDRAM Bank Disable Input:
When this pin is pulled LOW, outputs SDRAM0:3
will be disabled to a LOW state.
Crystal Connection or External Reference Frequency Input:
Connect to
either a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Power Connection:
Core Power supply. Connect to 3.3V supply.
Power Connection:
Power supply for the USB output. Connect to 3.3V or 2.5V
supply.
Power Connection:
Power supply for the CPU outputs. Connect to 3.3V or
2.5V supply.
Power Connection:
Power supply for the SDRAM outputs. Connect to 3.3V
or 2.5V supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDRAM0:3
FS0:1
SS%0:1
USBCLK
O
I
I
O
SSON#
USBCLKEN
REF
SDEN
X1
X2
VDDCORE
VDDU
VDDC
VDDS
GND
17
28
2
13
4
5
1, 12
25
22
8
3,11, 19, 27
I
I
O
I
I
I
P
P
P
P
G
Document #: 38-07268 Rev. *B
Page 2 of 10
CY24242
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in
Figure 1.
As shown in
Figure 1,
a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where
P
is the percentage of deviation and
F
is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the center
frequency.
Figure 2
details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the SMBus data stream.
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
-SS%
Frequency Span (MHz)
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
MIN. (–0.5%)
Figure 2. Typical Modulation Profile
Document #: 38-07268 Rev. *B
Page 3 of 10
100%
CY24242
Absolute Maximum Ratings
[4]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
.
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
2 (min.)
Unit
V
°C
°C
°C
kV
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
ESD
PROT
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Input ESD Protection
DC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V ± 10%
Parameter
Supply Current
I
DDQ3
I
DDQ2
Supply Current (3.3V)
Supply Current (2.5V)
CPUCLK = 100 MHz
Outputs Loaded
[4]
CPUCLK = 100 MHz
Outputs Loaded
[4]
GND-3
2.0
400
400
mA
mA
Description
Test Condition
Min.
Typ.
Max.
Unit
Logic Inputs
[5]
V
IL
V
IH
I
IL
I
IH
V
TH
C
LOAD
C
IN,X1
C
IN
C
OUT
L
IN
Input Low Voltage
Input High Voltage
Input Low Current
[6]
Input High Current
[6]
X1 Input Threshold Voltage
[1]
Load Capacitance, Imposed on
External Crystal
[7]
X1 Input Capacitance
[8]
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Pin X2 unconnected
Except X1 and X2
1.5
14
28
5
6
7
0.8
V
DD
+.3
–25
10
V
V
µA
µA
V
pF
pF
pF
pF
nH
Crystal Oscillator
Pin Capacitance/Inductance
Notes:
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. CY24242 logic inputs have internal pull-up resistors.
6. X1 input threshold voltage (typical) is V
DDQ
/2.
7. The CY24242 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07268 Rev. *B
Page 4 of 10
CY24242
AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DD
= V
DDQ3
= 3.3V±10%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, V
DDC
= 3.3V)
CPU = 66 MHz
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Period
High Time
Low Time
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at
1.5V
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.5V
Min.
15
5.2
5
0.4
0.4
45
–
–
–
–
–
–
–
–
15.5
–
–
3.2
3.2
55
250
CPU = 100 MHz
Typ. Max. Unit
–
–
–
–
–
–
–
10.5
–
–
3.2
3.2
55
250
ns
ns
ns
V/ns
V/ns
%
ps
10
3.0
2.8
0.4
0.4
45
–
Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V
t
SK
f
ST
Output Skew
–
–
–
–
250
3
–
–
–
–
250
3
ps
ms
Frequency Stabilization Assumes full supply voltage reached
from Power-up (cold
within 1 ms from power-up. Short
start)
cycles exist prior to frequency stabili-
zation.
AC Output Impedance
Average value during switching
transition. Used for determining series
termination value.
Z
o
–
20
–
–
20
–
Ω
SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, V
DDC
= 3.3V)
CPU = 66 MHz
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Period
High Time
Low Time
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at
1.5V
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/SDRAM outputs.
Measured on rising edge at 1.5V.
–
–
Min.
15
5.2
5
0.4
0.4
45
–
–
–
–
–
–
–
–
15.5
–
–
3.2
3.2
55
250
CPU = 100 MHz
Typ. Max. Unit
–
–
–
–
–
–
–
10.5
–
–
3.2
3.2
55
250
ns
ns
ns
V/ns
V/ns
%
ps
10
3.0
2.8
0.4
0.4
45
–
Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V
t
SK
t
SK
f
ST
Output Skew
CPU to SDRAM Clock
Skew
100
–
–
300
350
3
–
–
100
–
–
350
350
3
ps
ps
ms
Frequency Stabilization Assumes full supply voltage reached
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