Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2).
See
Table 1
on page 1.
A bypass delay capacitor at this output control Input Reference or Output
Banks phase relationships.
Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with both
the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the
divider ratios selected.
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs.
See
Table 2
on page 4.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs.
See
Table 2
on page 4.
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs.
See
Table 2
on page 4.
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output.
See
Table 1
on page 1.
VCO Divider Select Input. When set LOW, the VCO output is divided by 2.
When set HIGH, the divider is bypassed.
See
Table 1
on page 1.
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL
is bypassed.
Reference Select Input. When HIGH, the PECL inputs are selected. When
LOW, TCLK[0:1] are selected.
TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1
is selected.
Master Reset or Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to enable or
disable individual outputs. This provides flexibility in power management.
3.3V Power Supply for Output Clock Buffers.
3.3V Supply for PLL.
Common Ground.
Description
44, 46, 48, 50 QA(3:0)
32, 34, 36, 38 QB(3:0)
16, 18, 21, 23 QC(3:0)
29
FB_OUT
25
SYNC
VDDC
O
42, 43
40, 41
19, 20
5, 26, 27
52
31
6
7
8
2
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
FB_IN
PLL_EN
REF_SEL
TCLK_SEL
MR#/OE
I
I
I
I
I
I
I
I
I
I
14
3
4
17, 22, 28,
33,37, 45, 49
13
INV_CLK
SCLK
SDATA
VDDC
VDD
I
I
I
PU
PU
PU
1, 15, 24, 30, VSS
35, 39, 47, 51
Note
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their high frequency
filtering characteristics is cancelled by the lead inductance of the traces.
Document #: 38-07291 Rev. *C
Page 3 of 9
[+] Feedback
CY29973
Description
The CY29973 has an integrated PLL that provides low-skew and
low-jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs and an independent
PLL feedback output, FB_OUT, provide exceptional flexibility for
possible output configurations. The PLL is ensured stable
operation given that the VCO is configured to run between 200
MHz to 480 MHz. This allows a wide range of output frequencies
up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select inputs,
refer to
Table 1
on page 1. The VCO frequency is then divided
down to provide the required output frequencies. These dividers
are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see
Table 2.
For situations were the VCO needs to run at relatively
low frequencies and hence might not be stable, assert VCO_SEL
LOW to divide the VCO frequency by 2. This maintains the
desired output relationships, but provides an enhanced PLL lock
range.
The CY29973 is also capable of providing inverted output clocks.
When INV_CLK is asserted high, QC2 and QC3 output clocks
are inverted. These clocks could be used as feedback outputs to
the CY29973 or a second PLL device to generate early or late
clocks for a specific design. This inversion does not affect the
output to output skew.
Zero Delay Buffer
When used as a zero delay buffer the CY29973 is likely to be in
a nested clock tree application. For these applications the
CY29973 offers a low voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The CY29973 then can lock onto the
LVPECL reference and translate with near zero delay to low
skew outputs.
By using one of the outputs as a feedback to the PLL the propa-
gation delay through the device is eliminated. The PLL works to
align the output edge with the input reference edge thus
producing a near zero delay. The reference frequency affects the
static phase offset of the PLL and thus the relative delay between
the inputs and outputs. Because the static phase offset is a
function of the reference clock the Tpd of the CY29973 is a
function of the configuration used.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter’s
changed “on the fly’ their output clock periods will:
1. Contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the old
or new frequency that is being transitioned to.
2. Contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old or
new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt and
stretched clock pulses do not occur if the device logic levels of
any or all of the following pins changed “on the fly” while it is
operating: SELA, SELB, SELC, and VCO_SEL.
Table 2. Divider Table
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
QA
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
SELB1
0
0
1
1
0
0
1
1
SELB0
0
1
0
1
0
1
0
1
QB
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
Document #: 38-07291 Rev. *C
Page 4 of 9
[+] Feedback
CY29973
SYNC Output
In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system
synchronization. The CY29973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse,
one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of
the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for
the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under
some relationships the lower frequency clock could be used as a synchronizing signal.
Figure 1. SYNC Output for Different Input and Out Ratio
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