CY2DL1504
1:4 Differential LVDS Fanout Buffer
with Selectable Clock Input
Features
■
Functional Description
The CY2DL1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 differential LVDS fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2DL1504 can select between
LVPECL or LVDS input clock pairs using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The output enable
function allows the outputs to be asynchronously driven to a
high-impedance state. The device has a fully differential internal
architecture that is optimized to achieve low-additive jitter and
low-skew at operating frequencies of up to 1.5 GHz.
Select between low-voltage positive emitter-coupled logic
(LVPECL) or low-voltage differential signal (LVDS) input pairs
to distribute to four LVDS output pairs
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
Output enable and synchronous clock enable functions
20-pin thin shrunk small outline package (TSSOP)
2.5-V or 3.3-V operating voltage
[1]
Commercial and industrial operating temperature range
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Logic Block Diagram
V
DD
V
SS
Q0
Q0#
IN0
IN0#
IN1
IN1#
Q2
Q2#
IN_SEL
R
P
V
DD
R
P
Q1
Q1#
Q
D
Q3
Q3#
CLK_EN
V
DD
R
P
OE
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56312 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 29, 2011
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CY2DL1504
Contents
Pinout ................................................................................ 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions....................................................... 4
DC Electrical Specifications ............................................ 5
AC Electrical Specifications ............................................ 6
Ordering Information........................................................ 9
Ordering Code Definition............................................. 9
Package Diagram............................................................ 10
Acronyms ........................................................................ 11
Document Conventions .................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
11
12
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Document Number: 001-56312 Rev. *F
Page 2 of 14
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CY2DL1504
Pinout
Figure 1. Pin Diagram – CY2DL1504 20-Pin TSSOP Package
V
SS
CLK_EN
IN_SEL
IN0
IN0#
IN1
IN1#
OE
V
SS
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
Q0
Q0#
V
DD
Q1
Q1#
Q2
Q2#
V
SS
Q3
Q3#
CY2DL1504
17
16
15
14
13
12
11
Table 1. Pin Definitions
Pin No.
1,9,13
2
Pin Name
V
SS
CLK_EN
Input
Pin Type
Power
Ground
Synchronous clock enable. Low-voltage complementary metal oxide
semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL);
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are
held high
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
LVDS input clock. Active when IN_SEL = Low
LVDS complementary input clock. Active when IN_SEL = Low
LVPECL input clock. Active when IN_SEL = High
LVPECL complementary input clock. Active when IN_SEL = High
Output enable. LVCMOS/LVTTL;
When OE = Low, Q(0:3) and Q(0:3)# outputs are disabled (see I
OZ
)
Power supply
LVDS complementary output clocks
LVDS output clocks
Description
3
IN_SEL
Input
4
5
6
7
8
10,18
11,14,16,19
12,15,17,20
IN0
IN0#
IN1
IN1#
OE
V
DD
Q(0:3)#
Q(0:3)
Input
Input
Input
Input
Input
Power
Output
Output
Document Number: 001-56312 Rev. *F
Page 3 of 14
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CY2DL1504
Absolute Maximum Ratings
Parameter
V
DD
V
IN[2]
V
OUT[2]
T
S
ESD
HBM
L
U
UL–94
MSL
Supply voltage
Input voltage, relative to V
SS
DC output or I/O voltage, relative to V
SS
Storage temperature
Electrostatic discharge (ESD) protection
(Human body model)
Latch up
Flammability rating
Moisture sensitivity level
At 1/8 in.
Description
Condition
Nonfunctional
Nonfunctional
Nonfunctional
Nonfunctional
JEDEC STD 22-A114-B
Min
–0.5
–0.5
–0.5
–55
2000
Max
4.6
Lesser of 4.0
or V
DD
+ 0.4
Lesser of 4.0
or V
DD
+ 0.4
150
–
Unit
V
V
V
°C
V
Meets or exceeds JEDEC Spec
JESD78B IC latch up test
V–0
3
Operating Conditions
Parameter
V
DD
T
A
t
PU
Supply voltage
Ambient operating temperature
Power ramp time
Description
Condition
2.5-V supply
3.3-V supply
Commercial
Industrial
Power-up time for V
DD
to
reach minimum specified
voltage.
(Power ramp must be
monotonic)
Min
2.375
3.135
0
–40
0.05
Max
2.625
3.465
70
85
500
Unit
V
V
°C
°C
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-56312 Rev. *F
Page 4 of 14
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CY2DL1504
DC Electrical Specifications
(V
DD
= 3.3 V ± 5% or 2.5 V ± 5%; T
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
I
DD
V
IH1
Description
Operating supply current
Input high voltage,
LVDS and LVPECL input clocks,
IN0, IN0#, IN1, and IN1#
Input low voltage,
LVDS and LVPECL input clocks,
IN0, IN0#, IN1, and IN1#
Input high voltage,
CLK_EN, IN_SEL, and OE
Input low voltage,
CLK_EN, IN_SEL, and OE
Input high voltage,
CLK_EN, IN_SEL, and OE
Input low voltage,
CLK_EN, IN_SEL, and OE
LVDS input differential amplitude
LVPECL input differential amplitude
Input common mode voltage
Input high current, All inputs
Input low current, All inputs
V
DD
= 3.3 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 2.5 V
See
Figure 3
on page 7
See
Figure 3
on page 7
See
Figure 3
on page 7
Input = V
DD[6]
Input =
V
SS[6]
Condition
All LVDS outputs terminated with a load of
100
Ω
[3, 4]
Min
–
–
Max
61
V
DD
+ 0.3
Unit
mA
V
V
IL1
–0.3
–
V
V
IH2
V
IL2
V
IH3
V
IL3
V
ID_LVDS[5]
V
ID_LVPECL[5]
V
ICM
I
IH
I
IL
V
PP
V
OCM
ΔV
OCM
I
OZ
R
P
2.0
–0.3
1.7
–0.3
0.4
0.4
0.5
–
–150
250
1.125
–
–15
60
V
DD
+ 0.3
0.8
V
DD
+ 0.3
0.7
0.8
1.0
V
DD
– 0.2
150
–
470
1.375
50
15
165
V
V
V
V
V
V
V
μA
μA
mV
V
mV
μA
kΩ
LVDS differential output voltage peak V
DD
= 3.3 V or 2.5 V,
to Peak, Single-ended
R
TERM
= 100
Ω
between Q and Q# pairs
[3, 7]
LVDS differential output common
V
DD
= 3.3 V or 2.5 V,
mode voltage
R
TERM
= 100
Ω
between Q and Q# pairs
[3, 7]
Change in V
OCM
between
complementary output states
Output leakage current
V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100
Ω
between Q and Q# pairs
[3, 7]
OE = V
SS,
V
OUT
= 0.75V – 1.75V
Internal pull-up/pull-down resistance, CLK_EN has pull-up only
LVCMOS logic inputs
IN_SEL has pull-down only
OE has pull-up only
Input capacitance
Measured at 10 MHz; per pin
C
IN
–
3
pF
Notes
3. Refer to
Figure 2
on page 7.
4. I
DD
includes current that is dissipated externally in the output termination resistors.
5. V
ID
minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with V
ID
minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to
Figure 4
on page 7.
Document Number: 001-56312 Rev. *F
Page 5 of 14
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