Latch-up Current.................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
(T
A
)
[4]
0
°
C to +70
°
C
−40
°
C to +85
°
C
−40
°
C to +85
°
C
−40
°
C to +125
°
C
V
CC
2.7V to 3.6V
CY62256VN Commercial
Industrial
Automotive-A
Automotive-E
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic CE Power
Down Current -
TTL Inputs
Automatic CE Power
Down Current- CMOS
Inputs
GND < V
IN
< V
CC
GND < V
IN
< V
CC
, Output
Disabled
V
CC
= 3.6V, I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l/Ind’l/Auto-A
Auto-E
Com’l/Ind’l/Auto-A
Auto-E
All Ranges
I
OH
=
−1.0
mA
I
OL
= 2.1 mA
Test Conditions
V
CC
= 2.7V
V
CC
= 2.7V
2.2
–0.5
–1
–10
–1
–10
11
100
-70
Min
2.4
0.4
V
CC
+ 0.3V
0.8
+1
+10
+1
+10
30
300
Typ
[2]
Max
Unit
V
V
V
V
μA
μA
μA
μA
mA
μA
V
CC
= 3.6V, CE > V
IH
,
All Ranges
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
V
CC
= 3.6V, CE > V
CC
– 0.3V Com’l
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V,
Ind’l/Auto-A
f=0
Auto-E
I
SB2
0.1
5
10
130
μA
Notes
3. V
IL
(min) = –2.0V for pulse durations of less than 20 ns.
4. T
A
is the “Instant-On” case temperature.
Document #: 001-06512 Rev. *B
Page 3 of 13
[+] Feedback
CY62256VN
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.0V
Max
6
8
Unit
pF
pF
Thermal Resistance
[5]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Figure 1. AC Test Loads and Waveforms
R1
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
10%
GND
< 5 ns
Equivalent to:
THÉVENIN EQUIVALENT
R
th
OUTPUT
V
th
ALL INPUT PULSES
90%
90%
10%
< 5 ns
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
SOIC
68.45
26.94
TSOPI
87.62
23.73
RTSOPI
87.62
23.73
Unit
°C/W
°C/W
Parameter
R1
R2
RTH
VTH
Value
1100
1500
645
1.750
Units
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.4V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V
Com’l
Ind’l/Auto-A
Auto-E
0
t
RC
Figure 2. Data Retention Waveform
DATA RETENTION MODE
V
CC
1.8V
t
CDR
CE
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed V
CC
+ 0.3V.
Conditions
[6]
Min
1.4
Typ
[2]
0.1
Max
3
6
50
Unit
V
μA
t
CDR[6]
t
R[5]
Chip Deselect to Data
Retention Time
Operation Recovery Time
ns
ns
V
DR
> 1.4V
1.8V
t
R
Document #: 001-06512 Rev. *B
Page 4 of 13
[+] Feedback
CY62256VN
Switching Characteristics
Over the Operating Range
[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to
Low-Z
[8]
10
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power Up
CE HIGH to Power Down
0
70
10
25
5
25
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
CY62256VN-70
Min
Max
Unit
Notes
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified I
OL
/I
OH
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
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