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CY7C1011CV33-12AXI

Description
2-Mbit (128 K × 16) Static RAM 360 mW (max) (Industrial and Automotive-A)
File Size409KB,17 Pages
ManufacturerCypress Semiconductor
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CY7C1011CV33-12AXI Overview

2-Mbit (128 K × 16) Static RAM 360 mW (max) (Industrial and Automotive-A)

CY7C1011CV33
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
Functional Description
The CY7C1011CV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
131,072 words by 16 bits. This device has an automatic power
down feature that significantly reduces power consumption when
deselected.
To write to the device, take CE and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
(I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
16
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
16
).
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE) HIGH. If BLE is LOW, then data from the
memory location specified by the address pins appear on I/O
0
to
I/O
7
. If Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. For more information, see the
Truth
Table on page 10
for a complete description of Read and Write
modes.
The input and output pins (I/O
0
through I/O
15
) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
Temperature ranges
Industrial: –40 °C to 85 °C
Automotive-A: –40 °C to 85 °C
Automotive-E: –40 °C to 125 °C
Pin and function compatible with CY7C1011BV33
High speed
t
AA
= 10 ns (Industrial and Automotive-A)
t
AA
= 12 ns (Automotive-E)
Low active power
360 mW (max) (Industrial and Automotive-A)
2.0 V data retention
Automatic power down when deselected
Independent control of upper and lower bits
Easy memory expansion with Chip Enable (CE) and Output
Enable (OE) features
Available in Pb-free 44-pin thin small outline package
(TSOP) II, 44-pin thin quad flat package (TQFP), and non
Pb-free 48-ball very fine-pitch ball grid array (VFBGA)
packages
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
128 K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
10
A
11
A
12
A
14
A
15
A
13
A
16
A
9
Cypress Semiconductor Corporation
Document Number: 38-05232 Rev. *L
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 7, 2011
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