CY7C1444AV33
CY7C1445AV33
36-Mbit (1 M × 36/2 M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Features
■
■
■
■
■
■
■
■
Functional Description
The CY7C1444AV33/CY7C1445AV33
[1]
SRAM integrates
1 M × 36/2 M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE
1
), depth-expansion chip
enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP, and
ADV), write enables (BW
X
, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or a
+2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3 V core power supply
2.5 V/3.3 V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1444AV33,
CY7C1445AV33
available
in
JEDEC-standard Pb-free 100-pin TQFP package and Pb-free
and non Pb-free 165-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
■
■
■
■
■
■
■
■
Note
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05352 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 25, 2011
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table
(MODE = Floating or V
DD
) ................................................ 8
Linear Burst Address Table (MODE = GND) .................. 8
ZZ Mode Electrical Characteristics ................................. 8
Truth Table ........................................................................ 9
Partial Truth Table for Read/Write ................................ 10
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
TAP Controller State Diagram ....................................... 11
Test Access Port (TAP) ............................................. 11
TAP Controller Block Diagram ...................................... 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 12
TAP Timing ...................................................................... 13
TAP AC Switching Characteristics ............................... 13
3.3 V TAP AC Test Conditions ....................................... 14
3.3 V TAP AC Output Load Equivalent ......................... 14
2.5 V TAP AC Test Conditions ....................................... 14
2.5 V TAP AC Output Load Equivalent ......................... 14
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 14
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 15
Identification Codes ....................................................... 15
165-ball FBGA Boundary Scan Order ........................... 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Electrical Characteristics ............................................... 17
Capacitance .................................................................... 18
Thermal Resistance ........................................................ 18
AC Test Loads and Waveforms ..................................... 18
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Read Cycle Timing .................................................... 20
Write Cycle Timing .................................................... 21
Read/Write Cycle Timing ........................................... 22
ZZ Mode Timing ........................................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Document Number: 38-05352 Rev. *H
Page 3 of 29
[+] Feedback
ADI Reference Circuit
京公网安备 11010802033920号
EEWORLD
