CY7C1486BV33 datasheet, PDF - EEWORLD Datasheet

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CY7C1486BV33: Description72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM; File Size745KB，36 Pages; ManufacturerCypress Semiconductor

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CY7C1486BV33 Overview

72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

Pipelined Sync SRAM

72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM

Features

■

Functional Description

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

SRAM integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

), depth-expansion

Chip Enables (CE

and CE

), Burst Control inputs (ADSC,

ADSP, and ADV), Write Enables (BW

, and BWE), and Global

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at the rising edge of

the clock when either address strobe processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst

addresses may be internally generated as controlled by the

advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see sections

Pin Definitions on page 8

and

Truth

Table on page 11

for further details). Write cycles can be one to

two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

operates from a +3.3 V core power supply while all outputs may

operate with either a +2.5 or +3.3 V supply. All inputs and outputs

are JEDEC standard JESD8-5 compatible. For best practices

recommendations, refer to the Cypress application note

AN1064

“SRAM System Guidelines”.

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

3.3 V core power supply

2.5 V/3.3 V I/O operation

Fast clock-to-output times

❐

3.0 ns (for 250 MHz device)

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480BV33, CY7C1482BV33 available in JEDEC-

standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free

and non Pb-free 165-ball fine-pitch ball grid array (FBGA)

package. CY7C1486BV33 available in Pb-free and

non-Pb-free 209-ball FBGA package

IEEE 1149.1 JTAG-compatible boundary scan

“ZZ” sleep mode option

■

Selection Guide

Description

Maximum access time

Maximum operating current

Maximum CMOS standby current

250 MHz

3.0

500

120

200 MHz

3.0

500

120

167 MHz

3.4

450

120

Unit

Cypress Semiconductor Corporation

Document Number: 001-15145 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 30, 2011

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