Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 900 V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................. > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0 °C to +70 °C
V
CC
5 V
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power Down
Current—TTL Inputs
Automatic CE Power Down
Current—CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max, I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
Max V
CC
, CE > V
IH
, V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
Max V
CC
, CE > V
CC
0.3 V,
V
IN
> V
CC
0.3 V or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min, I
OH
=
4.0
mA
V
CC
= Min, I
OL
= 8.0 mA
-15
Min
2.4
–
2.2
0.5
5
5
–
–
–
Max
–
0.4
V
CC
+ 0.3 V
0.8
+5
+5
145
30
10
Unit
V
V
V
V
A
A
mA
mA
mA
Capacitance
Parameter
C
IN [3]
C
OUT [3]
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= 5.0 V
Max
8
10
Unit
pF
pF
Notes
1. Minimum voltage is equal to –2.0 V for pulse durations of less than 20 ns.
2. T
A
is the case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05047 Rev. *H
Page 4 of 12
[+] Feedback
CY7C192
Figure 2. AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
R1 481
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
R1 481
3.0 V
GND
10%
ALL INPUT PULSES
90%
90%
10%
< 3 ns
< 3 ns
Equivalent to:
THÉVENIN EQUIVALENT
167
OUTPUT
1.73 V
(a)
(b)
Switching Characteristics
Over the Operating Range
Parameter
[4]
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[7]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
[5]
WE LOW to High Z
[5, 6]
15
10
10
0
0
9
9
0
3
–
–
–
–
–
–
–
–
–
–
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[5]
CE HIGH to High Z
[5, 6]
CE LOW to Power Up
CE HIGH to Power Down
15
–
3
–
3
–
0
–
–
15
–
15
–
7
–
15
ns
ns
ns
ns
ns
ns
ns
ns
Description
-15
Min
Max
Unit
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
5. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZW\E
is less than t
LZWE
for any given device. These parameters are guaranteed by design and
not 100% tested.
6. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of
Figure 2.
Transition is measured
500
mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
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