CY8C21123, CY8C21223, CY8C21323
PSoC
®
Mixed Signal Array
Features
■
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Low power at High Speed
❐
2.4V to 5.25V Operating Voltage
❐
Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
❐
Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
❐
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
❐
Full Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐
Complex Peripherals by Combining Blocks
Flexible On-Chip Memory
❐
4K Flash Program Storage 50,000 Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Complete Development Tools
™
❐
Free Development Software (PSoC Designer )
❐
Full Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128 Bytes Trace Memory
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
❐
25 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to Eight Analog Inputs on GPIO
❐
Configurable Interrupt on all GPIO
Additional System Resources
2
❐
I C™ Master, Slave and MultiMaster to 400 kHz
❐
Watchdog and Sleep Timers
❐
User Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
Logic Block Diagram
Port 1
Port 0
■
PSoC
CORE
SystemBus
Global Digital Interconnect
Global Analog Interconnect
Flash
Sleep and
Watchdog
SRAM
Interrupt
Controller
SROM
■
CPU Core
(M8C)
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
ANALOG SYSTEM
Analog
PSoC Block
Array
Analog
Ref.
■
■
Digital
Clocks
POR and LVD
I2C
System Resets
■
Sw itch
Mode
Pump
Internal
Voltage
Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12022 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 22, 2008
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CY8C21123, CY8C21223, CY8C21323
PSoC
®
Functional Overview
The PSoC
®
family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, as shown in
Figure 1,
consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
Digital System
The Digital System consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral
configurations include:
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity (up to four)
SPI master and slave
I2C slave, master, MultiMaster (one available as a System
Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to four)
Pseudo Random Sequence Generators (8 to 32 bit)
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal arrays,
I2C functionality for implementing an I2C master, slave, Multi-
Master, an internal voltage reference that provides an absolute
value of 1.3V to a number of PSoC subsystems, a switch mode
pump (SMP) that generates normal operating voltages off a
single battery cell, and various system resets supported by the
M8C.
The Digital System consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in
Table 1
on page 3.
Figure 1. Digital System Block Diagram
Port 1
Port 0
DigitalClocks
FromCore
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12022 Rev. *H
Page 2 of 37
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Analog System
The Analog System consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■
■
■
■
Additional System Resources
System Resources, some of which listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■
Analog-to-digital converters (single or dual, with 8-bit
resolution)
Pin-to-pin comparators (one)
Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
1.3V reference (as a System Resource)
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
■
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
The number of blocks is on the device family which is detailed in
Table 1.
Figure 2. CY8C21x23 Analog System Block Diagram
■
■
■
PSoC Device Characteristics
Array Input
Configuration
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or
4 analog blocks.
Table 1
lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted.
Table 1. PSoC Device Characteristics
Digital
IO
ACI0[1:0]
ACI1[1:0]
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
16
8
4
4
4
4
0
12
12
48
12
28
8
28
4
4
2
2
0
0
0
4
4
2
2
2
2
0
12
12
6
6
4
a
4
a
3
b
2K
1
1K
1
PSoC Part
Number
ACOL1MUX
CY8C29x66
CY8C27x43
CY8C24x94
up to 4
64
up to 2
44
56
32K
Array
256 16K
Bytes
16K
256 4K
Bytes
512 8K
Bytes
256 4K
Bytes
512 8K
Bytes
ACE00
ASE10
ACE01
ASE11
CY8C24x23A up to 1
24
CY8C21x34
CY8C21x23
CY8C20x34
up to 1
28
16
up to 0
28
a.
Limited analog functionality
.
b. Two analog blocks and one CapSense.
Document Number: 38-12022 Rev. *H
Page 3 of 37
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Getting Started
The quickest path to understanding PSoC silicon is by reading
this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in depth information, along with
detailed programming information, refer the
PSoC Mixed Signal
Array Technical Reference Manual,
which can be found on
http://www.cypress.com/psoc.
For up to date Ordering, Packaging, and Electrical Specification
information, refer to the latest PSoC device data sheets on the
web at
http://www.cypress.com.
Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. Refer the PSoC Designer
Functional Flow diagram (Figure
3).
PSoC Designer helps the customer to select an operating
configuration for PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
Order >> Buy Kits at
http://www.cypress.com/shop,
click the
Online Store shopping cart icon at the bottom of the web page,
and click
PSoC (Programmable System-on-Chip)
to view a
current list of available items.
PSoC
TM
Designer
Graphical Designer
Interface
Context
Sensitive
Help
Commands
Results
Technical Training Modules
Free On-Demand PSoC Training modules are available for new
users to PSoC. Training modules cover designing, debugging,
advanced
analog,
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
http://www.cypress.com,
click on Support
located at the top of the web page, and select CYPros
Consultants.
Importable
Design
Database
Device
Database
Application
Database
Project
Database
User
Modules
Library
PSoC
Configuration
Sheet
PSoC
TM
Designer
Core
Engine
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at
http://www.cypress.com/support.
Manufacturing
Information
File
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com
and select Application Notes under
Documentation located in the center of the web page.
.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Document Number: 38-12022 Rev. *H
Page 4 of 37
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PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application specific code to flesh out
the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit C language and Assembly
language source code. You can also assemble, compile, link,
and build.
Assembler.
The macro assembler allows the seamless merging
of the assembly code with C code. The link libraries automatically
use absolute addressing or can be compiled in relative mode,
and linked with other software modules to get absolute
addressing.
C Language Compiler.
A C language compiler that supports
PSoC family devices is available. Even if you have never worked
in the C language before, the product helps you to quickly create
complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, which allows the designer to test the
program in a physical system while providing an internal view of
the PSoC device. Debugger commands allow the designer to
read the program and read and write data memory, read and
write IO registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online context-sensitive help for
the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
through the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
changes during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, can
implement a wide variety of user-selectable functions. Each
block has several registers that determine its function and
connectivity to other blocks, multiplexers, bus, and to the IO pins.
Iterative development cycles permit you to adapt the hardware
and the software. This substantially lowers the risk of having to
select a different part to meet the final design requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs,
Timers, Counters, UARTs, and other uncommon peripherals,
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run time. The API also provides optional interrupt service
routines that you can adapt as required.
Document Number: 38-12022 Rev. *H
Page 5 of 37
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