Automotive PSoC
Programmable System-on-Chip™
Features
■
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■
CY8C24894
®
Automotive Electronics Council (AEC) qualified
Powerful Harvard-architecture processor
❐
M8C processor speeds up to 24 MHz
❐
Two 8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 3.0 V to 5.25 V
❐
Automotive temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks)
❐
Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐
Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse-width modulators
(PWMs)
• Cyclic redundancy check (CRC) and pseudo-random
sequence (PRS) modules
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
• Capacitive sensing application capability
Flexible on-chip memory
❐
16-KB flash program storage, 1000 erase/write cycles
❐
1-KB SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Programmable pin configurations
❐
25-mA sink, 10-mA drive on all GPIOs
❐
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐
Up to 47 analog inputs on GPIOs
❐
Two 30-mA analog outputs on GPIOs
❐
Configurable interrupt on all GPIOs
Precision, programmable clocking
❐
Internal ±4% 24/48 MHz oscillator
❐
Internal low-speed, low-power oscillator for watchdog and
sleep functionality
❐
Optional external oscillator, up to 24 MHz
Additional system resources
2
❐
I C slave, master, or multimaster operation up to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable LVD
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full-featured in-circuit emulator (ICE) and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128-KB trace memory
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■
Logic Block Diagram
Port 7
Port 5
Port4
Port 3
Port 2
Port 1
Port 0 Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
Flash16K
Sleep and
Watchdog
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM
CPU Core (M8C)
Clock Sources
(Includes IMO and ILO)
■
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
■
Digital
2
Decimator
Clocks MACs
Type2
I2C
POR and LVD
System Resets
Internal
Voltage
Ref
.
Analog
Input
Muxing
SYSTEM RESOURCES
■
Errata:
For information on silicon errata, see
“Errata”
on page 46. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-53754 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 18, 2017
CY8C24894
Contents
PSoC Functional Overview.............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started.................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library.......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 6
PSoC Designer Software Subsystems........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules.............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug....................................... 7
Pinouts .............................................................................. 8
56-Pin Part Pinout (with XRES pin) ............................ 8
Registers ........................................................................... 9
Register Conventions .................................................. 9
Register Mapping Tables ............................................ 9
Register Map Bank 0 Table: User Space ................. 10
Register Map Bank 1 Table: Configuration Space ... 11
Electrical Specifications ................................................ 12
Absolute Maximum Ratings....................................... 13
Operating Temperature ............................................. 13
DC Electrical Characteristics..................................... 14
AC Electrical Characteristics ..................................... 27
Packaging Information...................................................
Thermal Impedances.................................................
Solder Reflow Specifications.....................................
Tape and Reel Information........................................
Development Tool Selection .........................................
Software ....................................................................
Development Kits ......................................................
Evaluation Tools........................................................
Device Programmers.................................................
Accessories (Emulation and Programming) ..............
Ordering Information......................................................
Ordering Code Definitions .........................................
Acronyms ........................................................................
Reference Documents....................................................
Document Conventions .................................................
Units of Measure .......................................................
Numeric Conventions ................................................
Glossary ..........................................................................
Errata ...............................................................................
Part Numbers Affected ..............................................
CY8C24x94 Errata Summary....................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Document Number: 001-53754 Rev. *J
Page 2 of 51
CY8C24894
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. All PSoC family
devices are designed to replace traditional microcontroller units
(MCUs), system ICs, and the numerous discrete components
that surround them. Configurable analog, digital, and inter-
connect circuitry enable a high level of integration in a host of
industrial, consumer, and communication applications.
This architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, Flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
The PSoC architecture, as illustrated in the
Logic Block Diagram
on page 1,
is comprised of four main areas: PSoc Core, digital
system, analog system, and system resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC CY8C24x94 devices can
have up to seven I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
six analog blocks.
The Digital System
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource used alone or combined with other
blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are
called user modules.
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four-MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real-time embedded events.
Program execution is timed and protected using the included
sleep timer and watchdog timer (WDT).
Memory encompasses 16 KB of flash for program storage, 1 KB
of SRAM for data storage, and up to 2 KB of emulated EEPROM
using the flash. Program flash has four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO) accurate to
±4% over temperature and voltage. The 24-MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32-kHz internal low-speed oscillator (ILO) is provided for the
sleep timer and WDT. The clocks, together with programmable
clock dividers (as system resources), provide the flexibility to
integrate almost any timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital resources,
and analog resources of the device. Each pin’s drive mode may
be selected from eight options, allowing great flexibility in
external interfacing. Every pin is also capable of generating a
system interrupt.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
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■
PWMs (8- to 32-bit)
PWMs with Dead band (8- to 24-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
Full- or half-duplex 8-bit UART with selectable parity
SPI master and slave
I
2
C master, slave, or multimaster (implemented in a dedicated
I
2
C block)
Cyclic redundancy checker/generator (16-bit)
Infrared Data Association (IrDA)
PRS generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow signal multiplexing and performing logic opera-
tions. This configurability frees your designs from the constraints
of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in
Table 1 on page 5.
Document Number: 001-53754 Rev. *J
Page 3 of 51
CY8C24894
The Analog System
The analog system is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
■
Figure 2. Analog System Block Diagram
A ll IO
(E x c e p t P o r t 7 )
P 0 [7 ]
P 0 [5 ]
P 0 [3 ]
P 0 [1 ]
AGNDIn RefIn
Mux Bus
Analog
P 0 [6 ]
P 0 [4 ]
P 0 [2 ]
P 0 [0 ]
P 2 [6 ]
ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta-sigma, or successive approximation register
(SAR))
Filters (two- and four-pole band pass, low pass, and notch)
Amplifiers (up to two, with selectable gain to 48x)
Instrumentation amplifiers (one with selectable gain to 93x)
Comparators (up to two, with 16 selectable thresholds)
DACs (up to two, with 6- to 9-bit resolution)
Multiplying DACs (up to two, with 6- to 9-bit resolution)
High current output drivers (two with 30-mA drive)
1.3-V reference (as a system resource)
DTMF Dialer
Modulators
Correlators
Peak Detectors
Many other topologies possible
P 2 [3 ]
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P 2 [4 ]
P 2 [2 ]
P 2 [0 ]
P 2 [1 ]
A C I 0 [1 :0 ]
A C I 1 [1 :0 ]
A r r a y In p u t
C o n f ig u r a t io n
B lo c k
A rray
AC B00
A SC 10
ASD20
A C B 01
A SD 11
A SC 21
A n a lo g R e f e r e n c e
In t e r f a c e t o
D ig it a l S y s t e m
R e fH i
R e fL o
AGND
R e fe r e n c e
G e n e ra to rs
A G N D In
R e fIn
B andgap
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in
Figure 2.
M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .)
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and ADCs. It can be split into two sections for simul-
taneous dual-channel processing. An additional 8:1 analog input
multiplexer provides a second path to bring Port 0 pins to the
analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Trackpad, finger sensing.
Chip-wide mux that allows analog input from up to 47 I/O pins.
Crosspoint connection between any I/O pin combination.
Document Number: 001-53754 Rev. *J
Page 4 of 51
CY8C24894
Additional System Resources
System resources provide additional capability useful for
complete systems. Additional resources include a multiplier,
decimator, LVD, and power-on reset (POR). Brief statements
describing the merits of each resource follow.
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including creation of Delta-
Sigma ADCs.
The I
2
C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
An internal 1.3-V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
Versatile analog multiplexer system.
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog
blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet is
shown in the highlighted row of the table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
[1]
CY8C28xxx
CY8C27x43
CY8C24x94
[1]
CY8C24x23A
[1]
CY8C23x33
CY8C22x45
[1]
CY8C21x45
[1]
CY8C21x34
[1]
CY8C21x23
CY8C20x34
[1]
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[2]
12
6
6
4
6
[2]
6
[2]
4
[2]
4
[2]
3
[2,3]
3
[2,3]
SRAM
Size
2K
1K
256
1K
256
256
1K
512
512
256
512
up to 2 K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
16 K
8K
8K
4K
8K
up to 32 K
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
3. Two analog blocks and one CapSense
®
block.
Document Number: 001-53754 Rev. *J
Page 5 of 51
Embedded System
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