Programmable System-on-Chip (PSoC )
General Description
PSoC
®
5: CY8C52 Family Datasheet
®
With its unique array of configurable blocks, PSoC
®
5 is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including inter-
faces such as USB and multimaster I
2
C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic
array, flexible routing to all I/O pins, and a high-performance 32-bit ARM
®
Cortex™-M3 microprocessor core. Designers can easily
create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical
schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration
while easily accommodating last minute design changes through simple firmware updates.
Library of standard peripherals
Features
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
32-bit ARM Cortex-M3 CPU core
• SPI, UART, and I
2
C
DC to 40 MHz operation
• Many others available in catalog
Flash program memory, up to 256 KB, 100,000 write cycles,
Library of advanced peripherals
20-year retention and multiple security features
• Cyclic redundancy check (CRC)
Up to 64 KB SRAM memory
• Pseudo random sequence (PRS) generator
128 bytes of cache memory
• Local interconnect network (LIN) bus 2.0
2-KB electrically erasable programmable read-only memory
• Quadrature decoder
(EEPROM) memory, 1 million cycles, and 20 years retention
Analog peripherals (2.7 V
V
DDA
5.5 V)
24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
1.024 V ±1% internal voltage reference
• Programmable chained descriptors and priorities
Successive approximation register (SAR) analog-to-digital
converter (ADC), 12-bit at 700 ksps
• High bandwidth 32-bit transfer support
One 8-bit, 5.5-Msps current DAC (IDAC) or 1-Msps voltage
Low voltage, ultra low power
DAC (VDAC)
Operating voltage range: 2.7 V to 5.5 V
Two comparators with 95-ns response time
6 mA at 6 MHz
CapSense support
Low power modes including:
Programming, debug, and trace
• 2-µA sleep mode
Serial wire debug (SWD) and single-wire viewer (SWV)
• 300-nA hibernate mode with RAM retention
interfaces
Versatile I/O system
Cortex-M3 flash patch and breakpoint (FPB) block
46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs))
Cortex-M3 data watchpoint and trace (DWT) generates data
Any GPIO to any digital or analog peripheral routability
trace information
LCD direct drive from any GPIO, up to 46 × 16 segments
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
®
used for printf-style debugging
CapSense support from any GPIO
1.2 V to 5.5 V I/O interface voltages, up to four domains
DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface
Maskable, independent IRQ on any pin or port
2
Schmitt trigger transistor-transistor logic (TTL) inputs
Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
All GPIOs configurable as open drain high/low, pull up/down,
High-Z, or strong output
Precision, programmable clocking
25 mA sink on SIO
3 to 24 MHz internal oscillator over full temperature and
voltage range
Digital peripherals
4 to 25 MHz crystal oscillator for crystal PPM accuracy
20 to 24 programmable
logic device (PLD)
based universal
Internal PLL clock generation up to 40 MHz
digital blocks (UDBs)
32.768 kHz watch crystal oscillator
Full-Speed (FS) USB 2.0 12 Mbps using a 24 MHz external
Low power internal oscillator at 1, 33, and 100 kHz
oscillator
Four 16-bit configurable timer, counter, and PWM blocks
Temperature and packaging
–40 °C to +85 °C degrees industrial temperature
68-pin QFN and 100-pin TQFP package options
Cypress Semiconductor Corporation
Document Number: 001-66236 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 15, 2012
PSoC
®
5: CY8C52 Family Datasheet
Contents
1. Architectural Overview ................................................. 3
2. Pinouts ........................................................................... 5
3. Pin Descriptions ............................................................ 8
4. CPU ................................................................................. 9
4.1 ARM Cortex-M3 CPU .............................................9
4.2 Cache Controller ..................................................11
4.3 DMA and PHUB ...................................................11
4.4 Interrupt Controller ...............................................14
5. Memory ......................................................................... 16
5.1 Static RAM ...........................................................16
5.2 Flash Program Memory ........................................16
5.3 Flash Security .......................................................16
5.4 EEPROM ..............................................................16
5.5 Memory Map ........................................................17
6. System Integration ...................................................... 18
6.1 Clocking System ...................................................18
6.2 Power System ......................................................21
6.3 Reset ....................................................................24
6.4 I/O System and Routing .......................................25
7. Digital Subsystem ....................................................... 32
7.1 Example Peripherals ............................................32
7.2 Universal Digital Block ..........................................36
7.3 UDB Array Description .........................................39
7.4 DSI Routing Interface Description ........................39
7.5 USB ......................................................................41
7.6 Timers, Counters, and PWMs ..............................41
7.7 I
2
C ........................................................................42
8. Analog Subsystem ...................................................... 43
8.1 Analog Routing .....................................................44
8.2 Successive Approximation ADC ...........................46
8.3 Comparators .........................................................46
8.4 LCD Direct Drive ..................................................47
8.5 CapSense .............................................................48
8.6 Temp Sensor ........................................................48
8.7 DAC ......................................................................48
9. Programming, Debug Interfaces, Resources ............ 49
9.1 Debug Port Acquisition .........................................49
9.2 SWD Interface ......................................................49
9.3 Debug Features ....................................................51
9.4 Trace Features .....................................................51
9.5 SWV Interface ......................................................51
9.6 Programming Features .........................................51
9.7 Device Security ....................................................51
10. Development Support ............................................... 52
10.1 Documentation ...................................................52
10.2 Online .................................................................52
10.3 Tools ...................................................................52
11. Electrical Specifications ........................................... 53
11.1 Absolute Maximum Ratings ................................53
11.2 Device Level Specifications ................................54
11.3 Power Regulators ...............................................56
11.4 Inputs and Outputs .............................................57
11.5 Analog Peripherals .............................................66
11.1 Digital Peripherals ..............................................78
11.2 Memory ..............................................................81
11.3 PSoC System Resources ...................................83
11.4 Clocking ..............................................................85
12. Ordering Information ................................................. 89
12.1 Part Numbering Conventions .............................89
13. Packaging ................................................................... 90
14. Acronyms ................................................................... 92
15. Reference Documents ............................................... 93
16. Document Conventions ............................................ 94
16.1 Units of Measure ................................................94
17. Revision History ........................................................ 95
18. Sales, Solutions, and Legal Information ................. 97
Document Number: 001-66236 Rev. *D
Page 2 of 97
PSoC
®
5: CY8C52 Family Datasheet
1. Architectural Overview
Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
GPIOs
System Wide
Resources
Usage Example for UDB
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
Sequencer
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16 -Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
4 to 25 MHz
( Optional
)
I2C
Master/
Slave
SIO
22
UDB
UDB
Clock Tree
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
8- Bit
Timer
Logic
UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
32.768 KHz
( Optional
)
RTC
Timer
System Bus
Memory System
WDT
and
Wake
GPIOs
EEPROM
FLASH
ILO
Cache
PHUB
DMA
Debug
Trace
SRAM
CPU System
8051or
Cortex M3 CPU
Interrupt
Controller
Program &
Debug
Program
Clocking System
Analog System
SIOs
Power Management
System
LCD Direct
Drive
POR and
LVD
Sleep
Power
2.7 to
5.5 V
1.8 V LDO
Temperature
Sensor
CapSense
DAC
ADC
SAR
ADC
GPIOs
+
2x
CMP
-
Figure 1-1
on page 3 illustrates the major components of the
CY8C52 family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Document Number: 001-66236 Rev. *D
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
Page 3 of 97
GPIOs
GPIOs
GPIOs
PSoC
®
5: CY8C52 Family Datasheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C52 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I
2
C slave, master, and multimaster
and Full-Speed USB.
For more details on the peripherals see the
“Example
Peripherals”
section on page 32 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 32 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
Analog muxes
Comparators
Voltage references
ADC
DAC
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C52 family offers a SAR ADC. Featuring 12-bit
conversions at up to 700 k samples per second, it also offers low
nonlinearity and offset errors. It is well suited for a variety of
higher speed analog applications.
A high-speed voltage or current DAC supports 8-bit output
signals at an update rate of 5.5 Msps in IDAC and 1 Msps in
VDAC. It can be routed out of any GPIO pin. You can create
higher resolution voltage PWM DAC outputs using the UDB
array. This can be used to create a pulse width modulated (PWM)
DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each
UDB support PWM, PRS, or delta-sigma algorithms with
programmable widths.
In addition to the ADC and DAC, the analog subsystem provides
multiple comparators. See the
“Analog Subsystem”
section on
page 43 of this data sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 40 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, cache,
and interrupt controller. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The presence of cache improves the access speed of
instructions by the CPU.
PSoC’s nonvolatile subsystem consists of flash and
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
DDIO
pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
OH
to be set independently of V
DDIO
when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
2
C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB, the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the
“I/O System and Routing”
section on page 25 of this
data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system and has 5% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 40 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low-speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768 kHz external watch crystal is also
supported for use in RTC applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C52 family supports a wide supply operating range from
2.7 to 5.5 V. This allows operation from regulated supplies such
as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of
battery types.
PSoC supports a wide range of low power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 6 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 21 of this data sheet.
Document Number: 001-66236 Rev. *D
Page 4 of 97
PSoC
®
5: CY8C52 Family Datasheet
PSoC uses a SWD interface for programming, debug, and test.
Using this standard interface enables the designer to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. The Cortex-M3 debug and trace
modules include FPB, DWT, and ITM. These modules have
many features to help solve difficult debug and trace problems.
Details of the programming, test, and debugging interfaces are
discussed in the
“Programming, Debug Interfaces, Resources”
section on page 49 of this data sheet.
2. Pinouts
The VDDIO pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
Figure 2-1
and
Figure 2-2.
Using the VDDIO pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each VDDIO may sink up to 20 mA total to its
associated I/O pins and opamps, and each set of VDDIO
associated pins may sink up to 100 mA.
Figure 2-1. 68-pin QFN Part Pinout
[1]
P15[5] (GPIO)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO, SAR0REF)
VDDIO0
58
57
56
55
54
53
52
68
67
(GPIO) P2[6]
(GPIO) P2[7]
(SIO) P12[4]
(SIO) P12[5]
VSSD
[2]
DNU
VSSD
VSSD
VSSD
XRES
(SWDIO, GPIO) P1[0]
(SWDCK, GPIO) P1[1]
(GPIO) P1[2]
(SWV, GPIO) P1[3]
(GPIO) P1[4]
(GPIO) P1[5]
VDDIO1
66
65
64
63
62
61
60
59
P2[5] (GPIO)
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
Lines show VDDIO
to I/O supply
association
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
QFN
(TOP VIEW)
P0[3] (GPIO, EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO)
P12[0] (SIO)
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO3
18
19
20
21
22
23
24
25
26
27
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[2]
(USBIO, D+, SWDIO) P15[6]
[2]
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
MHZ XTAL: XO
Notes
1. The center pad on the QFN package should be connected to digital ground (V
SSD
) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
2. Pins labeled Do Not Use (DNU) must be left floating. USB pins on devices without USB are DNU.
Document Number: 001-66236 Rev. *D
Page 5 of 97
MHZ XTAL: XI
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
(GPIO) P3[5]
28
29
30
31
32
33
34
Power technology
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