CY8CLED16P01
Powerline Communication Solution
Features
Powerline Communication Solution
❐
Integrated Powerline Modem PHY
❐
Frequency Shift Keying Modulation
❐
Configurable baud rates up to 2400 bps
❐
Powerline Optimized Network Protocol
❐
Integrates Data Link, Transport, and Network Layers
❐
Supports Bidirectional Half Duplex Communication
❐
8-bit CRC Error Detection to Minimize Data Loss
2
❐
I C enabled Powerline Application Layer
2
❐
Supports I C Frequencies of 50, 100, and 400 kHz
❐
Reference Designs for 110V/240V AC and 12V/24V AC/DC
Powerlines
❐
Reference Designs comply with CENELEC EN
50065-1:2001 and FCC Part 15
■
HB LED Controller
❐
Configurable Dimmers Support up to 16 Independent LED
Channels
❐
8 to 32 Bits of Resolution per Channel
❐
PrISM™ Modulation technology to reduce radiated EMI and
Low Frequency Blinking
❐
Additional communication interfaces for lighting control such
as DALI, DMX512 etc.
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Two 8x8 Multiply, 32-Bit Accumulate
®
■
Programmable System Resources (PSoC Blocks)
■
12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐
16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPI
TM
Masters or Slaves
• Connectable to all GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Flexible On-Chip Memory
❐
32 KB Flash Program Storage 50,000 Erase or Write Cycles
❐
2 KB SRAM Data Storage
❐
EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐
25 mA Sink, 10 mA Source on all GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐
Up to 12 Analog Inputs on GPIO
❐
Configurable Interrupt on all GPIO
❐
■
Additional System Resources
2
❐
I C Slave, Master, and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
Logic Block Diagram
Powerline Communication Solution
Embedded Application
Powerline
Network Protocol
Digital and Analog
Peripherals
PrISM, PWM etc.
Physical Layer
FSK Modem
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
Additional
Communication
Interface
DALI, DMX512
PLC Core
PSoC Core
Powerline Transceiver Packet
HB LED
Controller
AC/DC Powerline Coupling Circuit
(110V/240V AC, 12V/24V AC/DC etc.)
Powerline
Cypress Semiconductor Corporation
Document Number: 001-49263 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 05, 2009
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CY8CLED16P01
Programmable
System Resources
Modulation
Technology
CY8CLED16P01
1. PLC Functional Overview
The CY8CLED16P01 is an integrated Powerline Communication
(PLC) chip with the Powerline Modem PHY and Network
Protocol Stack running on the same device. Apart from the PLC
core, the CY8CLED16P01 also offers Cypress's revolutionary
PSoC technology that enables system designers to integrate
multiple functions on the same chip.
Figure 1-2. Physical Layer FSK Modem Block Diagram
Network Protocol
Digital
Receiver
Digital
Transmitter
Logic ‘1’ or
Logic ‘0’
Modulator
Square Wave
at FSK
Frequencies
Hysteresis
Comparator
Low Pass
Filter
Powerline Modem PHY
1.1 Robust Communication using Cypress’s PLC
Solution
Powerlines are available everywhere in the world and are a
widely available communication medium for PLC technology.
The pervasiveness of powerlines also makes it difficult to predict
the characteristics and operation of PLC products. Because of
the variable quality of powerlines around the world, imple-
menting robust communication has been an engineering
challenge for years. The Cypress PLC solution enables secure
and reliable communications. Cypress PLC features that enable
robust communication over powerlines include:
■
Local
Oscillator
External Low
Pass Filter
Correlator
IF Band
Pass Filter
Mixer
HF Band
Pass Filter
RX
Amplifier
Local
Oscillator
Transmitter
Programmable
Gain Amplifier
Integrated Powerline PHY modem with optimized filters and
amplifiers to work with lossy high voltage and low voltage
powerlines.
Powerline optimized network protocol that supports bidirec-
tional communication with acknowledgement-based signaling.
In case of data packet loss due to bursty noise on the powerline,
the transmitter has the capability to retransmit data.
The Powerline Network Protocol also supports an 8-bit CRC
for error detection and data packet retransmission.
A Carrier Sense Multiple Access (CSMA) scheme is built into
the network protocol that minimizes collisions between packet
transmissions on the powerline and supports multiple masters
and reliable communication on a bigger network.
Coupling Circuit
■
1.2.1 Transmitter Section
Digital data from the network layer is serialized by the digital
transmitter and fed as input to the modulator. The modulator
divides the local oscillator frequency by a definite factor
depending on whether the input data is high level logic ‘1’ or low
level logic ‘0’. It then generates a square wave at 133.3 kHz (logic
‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable
Gain Amplifier to generate FSK modulated signals. This enables
tunable amplification of the signal depending on the noise in the
channel. The logic ‘1’ frequency can also be configured as
130.4 kHz for wider FSK deviation.
1.2.2 Receiver Section
The incoming FSK signal from the powerline is input to a high
frequency (HF) band pass filter that filters out-of-band frequency
components and outputs a filtered signal within the desired
spectrum of 125 kHz to 140 kHz for further demodulation. The
mixer block multiplies the filtered FSK signals with a locally
generated signal to produce heterodyned frequencies.
The intermediate frequency (IF) band pass filters further remove
out-of-band noise as required for further demodulation. This
signal is fed to the correlator, which produces a DC component
(consisting of logic ‘1’ and ‘0’) and a higher frequency
component.
The output of the correlator is fed to a low pass filter (LPF) that
outputs only the demodulated digital data at 2400 baud and
suppresses all other higher frequency components generated in
the correlation process. The output of the LPF is digitized by the
hysteresis comparator. This eliminates the effects of correlator
delay and false logic triggers due to noise. The digital receiver
deserializes this data and outputs to the network layer for inter-
pretation.
■
■
1.2 Powerline Modem PHY
Figure 1-1. Physical Layer FSK Modem
Powerline Communication Solution
Embedded Application
Modulation
Technology
PrISM, PWM etc.
Powerline
Network Protocol
Digital and Analog
Peripherals
Physical Layer
FSK Modem
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
Additional
Communication
Interface
DALI, DMX512
PLC Core
PSoC Core
Powerline Transceiver Packet
HB LED
Controller
The physical layer of the Cypress PLC solution is implemented
using an FSK modem that enables half duplex communication
on any high voltage and low voltage powerline. This modem
supports raw data rates up to 2400 bps. A block diagram is
shown in
Figure 1-2.
Document Number: 001-49263 Rev. *E
CY8CLED16P01
Programmable
System Resources
Receiver
Page 2 of 46
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CY8CLED16P01
1.2.3 Coupling Circuit Reference Design
The coupling circuit couples low voltage signals from the
CY8CLED16P01 to the powerline. The topology of this circuit is
determined by the voltage on the powerline and design
constraints mandated by powerline usage regulations.
Cypress provides reference designs for a range of powerline
voltages including 110V/240V AC and 12V/24V AC/DC. The
CY8CLED16P01 is capable of data communication over other
AC/DC Powerlines as well with the appropriate external coupling
circuit. The 110V AC and 240V AC designs are compliant to the
following powerline usage regulations:
■
■
1.3.1 CSMA and Timing Parameters
■
CSMA – The protocol provides the random selection of a period
between 85 and 115 ms (out of seven possible values in this
range). Within this period, the Band-In-Use (BIU) detector must
indicate that the line is not in use, before attempting a trans-
mission.
BIU – A Band-In-Use detector, as defined under CENELEC EN
50065-1, is active whenever a signal that exceeds 86 dBμVrms
anywhere in the range 131.5 kHz to 133.5 kHz is present for
at least 4 ms. This threshold can be configured for different
end-system applications not requiring CENELEC
compliance.The modem tries to retransmit after every 85 to
115 ms when the band is in use. The transmitter times out after
1.1 seconds to 3 seconds (depending on the noise on the
Powerline) and generates an interrupt to indicate that the trans-
mitter was unable to acquire the powerline.
■
FCC Part 15 for North America
EN 50065-1:2001 for Europe
1.3 Network Protocol
Cypress’s powerline optimized network protocol performs the
functions of the data link, network, and transport layers in an
ISO/OSI-equivalent model.
Figure 1-3. Powerline Network Protocol
1.3.2 Powerline Transceiver Packet
The powerline network protocol defines a Powerline Transceiver
(PLT) packet structure, which is used for data transfers between
nodes across the powerline. Packet formation and data trans-
mission across the powerline network is implemented internally
in the CY8CLED16P01.
A PLT packet is divided into a variable length header (minimum
6 bytes to maximum 20 bytes, depending on address type),
variable length payload (minimum 0 bytes to maximum 31
bytes), and a packet CRC byte.
This packet (preceded by a one byte preamble "0xAB") is then
transmitted by the powerline modem PHY and the external
coupling circuit across the powerline.
The format of the PLT packet is shown in the following table.
Table 1-1. Powerline Transceiver (PLT) Packet Structure
Byte
Offset
7
6
5
4
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Payload (0 to 31 Bytes)
Powerline Transceiver Packet CRC
RSVD
Seq Num
SA
Type
Bit Offset
3
2
1
0
Powerline Communication Solution
Embedded Application
Modulation
Technology
PrISM, PWM etc.
Powerline
Network Protocol
Digital and Analog
Peripherals
Physical Layer
FSK Modem
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
Additional
Communication
Interface
DALI, DMX512
PLC Core
PSoC Core
Powerline Transceiver Packet
HB LED
Controller
CY8CLED16P01
Programmable
System Resources
The network protocol implemented on the CY8CLED16P01
supports the following features:
■
■
■
■
■
■
■
■
■
DA Type Service RSVD RSVD Response RSVD
Type
Bidirectional half duplex communication
Master-slave or peer-to-peer network topologies
Multiple masters on powerline network
8-bit logical addressing supports up to 256 powerline nodes
16-bit extended logical addressing supports up to 65536
powerline nodes
64-bit physical addressing supports up to
Carrier Sense Multiple Access (CSMA)
Full control over transmission parameters
❐
Acknowledged
❐
Unacknowledged
❐
Repeated Transmit
2
64
powerline nodes
Individual, broadcast or group mode addressing
Destination Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
Source Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
Command
Payload Length
Powerline Packet Header CRC
Document Number: 001-49263 Rev. *E
Page 3 of 46
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CY8CLED16P01
1.3.3 Packet Header
The packet header contains the first 6 bytes of the packet when
1-byte logical addressing is used. When 8-byte physical
addressing is used, the source and destination addresses each
contain 8 bytes. In this case, the header can consist of a
maximum of 20 bytes. Unused fields marked RSVD are for future
expansion and are transmitted as bit 0.
Table 1-2
describes the
PLT packet header fields in detail.
Table 1-2. Powerline Transceiver (PLT) Packet Header
Field
Name
SA Type
DA Type
No. of
Bits
1
2
Tag
Source
Address
Type
Description
0 – Logical Addressing
1 – Physical Addressing
■
■
Physical addressing: Every CY8CLED16P01 has a unique
64-bit physical address.
Group addressing: This is explained in the next section.
1.3.8 Group Membership
Group membership enables the user to multicast messages to
select groups. The CY8CLED16P01 supports two types of group
addressing:
■
Single Group Membership – The network protocol supports up
to 256 different groups on the network in this mode. In this
mode, each PLC node can only be part of a single group. For
example, multiple PLC nodes can be part of Group 131.
Multiple Group Membership – The network protocol supports
eight different groups in this mode and each PLC node can be
a part of multiple groups. For example, a single PLC node can
be a part of Group 3, Group 4, and Group 7 at the same time.
■
Service
Type
Response
1
1
Seq Num
Header
CRC
4
4
00 – Logical Addressing
Destination
01 – Group Addressing
Address
10 – Physical Addressing
Type
11 – Invalid
0 – Unacknowledged Messaging
1 – Acknowledged Messaging
Response 0 - Not an acknowledgement or
response packet
1 - Acknowledgement or response
packet
4-bit unique identifier for each
Sequence packet between source and desti-
Number
nation.
4-bit CRC value. This enables the
receiver to suspend receiving the
rest of the packet if its header is
corrupted
Both of these membership modes can also be used together for
group membership. For example, a single PLC node can be a
part of Group 131 and also multiple groups such as Group 3,
Group 4, and Group 7.
The group membership ID for broadcasting messages to all
nodes in the network is 0x00.
The service type is always set to Unacknowledgment Mode in
Group Addressing Mode. This is to avoid acknowledgment
flooding on the powerline during multicast.
1.3.9 Remote Commands
In addition to sending normal data over the Powerline, the
CY8CPLC10 can also send (and request) control information to
(and from) another node on the network. The type of remote
command to transmit is set by the TX_CommandID register and
when received, is stored in the RX_CommandID register.
When a control command (Command ID = 0x01 - 0x08 and 0x0C
- 0x0F) is received, the protocol will automatically process the
packet (if Lock_Configuration is '0'), respond to the initiator, and
notify the host of the successful transmission and reception.
When the send data command (ID 0x09) or request for data
command (ID 0x0A) is received, the protocol will reply with an
acknowledgment packet (if TX_Service_Type = '1'), and notify
the host of the new received data. If the initiator doesn't receive
the acknowledgment packet within 500ms, it will notify the host
of the no acknowledgment received condition.
When a response command (ID 0x0B) is received by the initiator
within 1.5s of sending the request for data command, the
protocol will notify the host of the successful transmission and
reception. If the response command is not received by the
initiator within 1.5s, it will notify the host of the no response
received condition.
The host is notified by updating the appropriate values in the
INT_Status register (including Status_Value_Change).
The command IDs 0x30-0xff can be used for custom commands
that would be processed by the external host (e.g. set an LED
color, get a temperature/voltage reading). The available remote
commands are described in
Table 1-3
on page 5 with the
respective Command IDs.
1.3.4 Payload
The packet payload has a length of 0 to 31 bytes. Payload
content is user defined and can be read or written through I
2
C.
1.3.5 Packet CRC
The last byte of the packet is an 8-bit CRC value used to check
packet data integrity. This CRC calculation includes the header
and payload portions of the packet and is in addition to the
powerline packet header CRC.
1.3.6 Sequence Numbering
The sequence number is increased for every new unique packet
transmitted. If in acknowledged mode and an acknowledgment
is not received for a given packet, that packet will be re-trans-
mitted (if TX_Retry > 0) with the same sequence number. If in
unacknowledged mode, the packet will be transmitted (TX_Retry
+ 1) times with the same sequence number.
If the receiver receives consecutive packets from the same
source address with the same sequence number and packet
CRC, it does not notify the host of the reception of the duplicate
packet. If in acknowledged mode, it still sends an acknowl-
edgment so that the transmitter knows that the packet was
received.
1.3.7 Addressing
The CY8CLED16P01 has three modes of addressing:
■
Logical addressing: Every CY8CLED16P01 node can have
either a 8-bit logical address or a 16-bit logical address. The
logical address of the PLC Node is set by the local application
or by a remote node on the Powerline.
Document Number: 001-49263 Rev. *E
Page 4 of 46
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CY8CLED16P01
Table 1-3. Remote Commands
Cmd ID
0x01
Command Name
SetRemote_TXEnable
Description
Payload (TX Data)
Response (RX Data)
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
Sets the TX Enable bit in the 0 - Disable Remote TX
PLC Mode Register. Rest of the 1 - Enable Remote TX
PLC Mode register is
unaffected
Set the Addressing to
Extended Addressing Mode
0 - Disable Extended
Addressing
1 - Enable Extended
Addressing
If Ext Address = 0,
Payload = 8-bit Logical
Address
If Ext Address = 1,
Payload = 16-bit
Logical Address
0x03
SetRemote_ExtendedAddr
0x04
SetRemote_LogicalAddr
Assigns the specified logical
address to the remote PLC
node
0x05
GetRemote_LogicalAddr
Get the Logical Address of the None
remote PLC node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
{If Ext Address = 0,
Response = 8-bit Logical
Address
If Ext Address = 1, Response
= 16-bit Logical Address}
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = 64-bit Physical
Address
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = Remote PLC
Mode register
If TX Enable = 0, Response =
None
If TX Enable = 1, Response =
Remote Version register
If Local Service Type = 0,
Response = None
If Local Service Type = 1,
Response = Ack
If Local Service Type = 1,
Response = Ack
Then, the remote node host
must send a
ResponseRemote_Data
command. The response must
be completely transmitted
within 1.5s of receiving the
request. Otherwise, the
requesting node will time out.
None
0x06
GetRemote_PhysicalAddr
Get the Physical Address of the None
remote PLC node
0x07
GetRemote_State
Request PLC_Mode Register
content from a Remote PLC
node
None
0x08
GetRemote_Version
Get the Version Number of the None
Remote Node
0x09
SendRemote_Data
Transmit data to a Remote
Node.
Payload = Local TX
Data
0x0A
RequestRemote_Data
Request data from a Remote
Node
Payload = Local TX
Data
0x0B
0x0C
ResponseRemote_Data
SetRemote_BIU
Transmit response data to a
Remote Node.
Payload = Local TX
Data
Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0,
ality at the remote node
1 - Disable Remote BIU Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
Document Number: 001-49263 Rev. *E
Page 5 of 46
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