DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720101
USB2.0 HOST CONTROLLER
The
µ
PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
µ
PD720101 is integrated 3 host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720101 User’s Manual: S16336E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling.
• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2
• Supports PCI Mobile Design Guide Revision 1.1
• Supports PCI-Bus Power Management Interface Specification release 1.1
• PCI bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
−
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see
µ
PD720101
User’s Manual.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
144-pin plastic LQFP (Fine pitch) (20
×
20)
144-pin plastic FBGA (12
×
12)
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PD720101GJ-UEN
µ
PD720101F1-EA8
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16265EJ4V0DS00 (4th edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark
shows major revised points.
2002
µ
PD720101
PCI Bus Interface
: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI
specification release 2.2. The number of enabled ports is set by bit in configuration
space.
Arbiter
OHCI Host Controller #1
OHCI Host Controller #2
EHCI Host Controller
Root Hub
PHY
INTA0
INTB0
INTC0
SMI0
: arbitrates among two OHCI host controller cores and one EHCI host controller core.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
: handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.
: handles USB hub function in host controller and controls connection (routing) between
host controller core and port.
: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
etc.
: is the PCI interrupt signal for OHCI Host Controller #1.
: is the PCI interrupt signal for OHCI Host Controller #2.
: is the PCI interrupt signal for EHCI Host Controller.
: is the interrupt signal which is specified by Open Host Controller Interface Specification
for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The
SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this
signal.
PME0
: is the interrupt signal which is specified by PCI-Bus Power Management Interface
Specification release 1.1. Wakeup signal of each host controller core appears at this
signal.
COMPARISON WITH THE
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PD720100A
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PD720100A
EHCI revision
EHCI
OHCI
Legacy support
Clock
Package
0.95
1
2
Parallel IRQ out support
48 MHz OSC or 30 MHz OSC/X’tal
176-pin BGA (FP) or 160-pin LQFP
1.0
1
2
No parallel IRQ support
48 MHz OSC or 30 MHz X’tal
144-pin BGA (FP) or 144-pin LQFP
µ
PD720101 (2nd generation)
Data Sheet S16265EJ4V0DS
3
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