• Products and Product Information are Subject to Change Without Notice • May 25, 2011
1
DATA SHEET
•
SC SERIES: MIS CHIP CAPACITORS
Table 1. MIS Capacitors Absolute Maximum Ratings
Parameter
Dielectric withstand voltage
Operating temperature
Storage temperature
Note:
Symbol
T
OP
T
STG
Minimum
–65
–65
Typical
100
Maximum
+200
+200
Units
V
°C
°C
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value.
CAUTION:
Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 2. MIS Chip Capacitors Electrical Specifications (Note 1)
Parameter
Capacitance
Temperature coefficient
Capacitance tolerance
Operating temperature
Dielectric withstand voltage
Insulation resistance
Leakage current
Note 1:
Performance is guaranteed only under the conditions listed in this Table.
Symbol
Test Condition
Min
0.8
Typical
50
Max
1000
+20
+200
Units
pF
ppm/°C
%
°C
V
MΩ
nA
–20
T
OP
–65
100
10
5
<1
Electrical and Mechanical Specifications
The absolute maximum ratings of the MIS chip capacitors are
provided in Table 1. Electrical specifications are provided in
Table
2.
A graph of typical insertion loss versus frequency is shown in
Figure 1. This data is taken from an actual test circuit with series
mounted beam-lead or chip capacitors on a 50
Ω
microstrip
transmission line. The apparent higher loss at lower frequencies
on the lower capacitance units is strictly due to the capacitive
reactance of the capacitor.
Table 3 provides a list of the available MIS chip capacitors (by part
number) and the capacitance and chip dimensions for each one.
Performance
Tests on typical MIS capacitors at the L and S bands show
insertion loss to be 1/2 to 1/3 that of equivalent ceramic type
capacitors, without any of the associated resonance problems.
Power tests indicate that the only limitation is the actual
breakdown voltage of the device.
Figure 2 illustrates the use of MIS capacitors in a typical Single-
Pole, Double-Throw (SPDT) circuit.
Package Dimensions
Figure 3 provides a visual representation of the capacitor chip
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