Ordering number : EN3356A
SANYO Semiconductors
DATA SHEET
CMOS IC
LC7185-8750
Overview
Functions
CB Transceiver PLL Frequency Synthesizer
and Controller
This 27 MHz band, PLL frequency synthesizer LSI chip is designed specifically for CB transceivers.
The specifications are suited for use in U.S.A.(FCC).
The LC7185-8750 incorporates PLL circuitry and a controller for CB applications on a single CMOS chip. The controller handles
the PLL circuitry, frequency data ROM, channel preset/recall RAM, and LED display driver. It also supports channel scan, channel
preset/recall, and emergency channel call.
Features
1. A built-in programmable divider for the 16 MHz VCO
2. Transmission is inhibited when the PLL is unlocked (digital lock monitor).
3. Direct channel 9 or 19 selection (sliding switch)
4. A 7-segment, 2-character LED display
5. ‘‘PA’’ is displayed in public announcement mode.
6. Output beep-tone control circuitry
7. Up to 5 channel settings can be stored in memory.
8. 4
× 3
key matrix implementation
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Symbol
V
DD
max
V
IN
1 max
V
IN
2 max
V
O
1 max
V
O
2 max
V
O
3 max
V
O
4 max
Output Current
I
O
1 max
I
O
2 max
I
O
3 max
I
O
4 max
Allowable power
dissipation
Operating temperature
Storage temperature
Pd max
Topr
Tstg
Conditions
Pin V
DD
Pins HOLD, TX
Input pins other than V
IN
1 max
Pins SA, SB, SC, SD, SE, SF, SG, D1, D2
Pins UL, BEEP
Pin PD
Output pins other than mentioned above
Pins SA, SB, SC, SD, SE, SF, SG
Pins D1, D2
Pins UL
Pin BEEP
(Ta
≤
85°C)
Ratings
–0.3 to +9.0
–0.3 to +15
–0.3 to V
DD
+0.3
–0.3 to +15
–0.3 to +15
–0.3 to V
DD
+0.3
–0.3 to V
DD
+0.3
0 to +30
0 to +10
0 to +20
0 to +10
350
–40 to +85
–55 to +125
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
mW
°C
°C
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1806 / 73098HA(II) / 5220TA No.3356-1/12
LC7185-8750
Allowable Operating Conditions
at Ta = –40 to +85°C, V
SS
= 0 V
Parameter
Supply voltage
Input high-level voltage
Symbol
V
DD
V
IH
1
V
IH
2
V
IH
3
V
IL
1
V
IL
2
V
IL
3
V
OUT
1
V
OUT
2
f
IN
1
f
IN
2
V
IN
1
V
IN
2
X’tal
Conditions
Pins HOLD, TX
Pin INIT
Pins KI1, KI2, KI3, KI4
Pins HOLD, TX
Pin INIT
Pins KI1, KI2, KI3, KI4
Pins SA, SB, SC, SD, SE, SF, SG, D1, D2
Pins UL, BEEP
Pin XIN (sine wave, capacitor coupled)
Pin PIN (sine wave, capacitor coupled)
Pin XIN (sine wave, capacitor coupled)
Pin PIN (sine wave, capacitor coupled)
Pins XIN, XOUT (CI
%
50
Ω)
min
5.0
0.7V
DD
3.2
0.6V
DD
0
0
0
0
0
1.0
10
0.5
0.15
5.0
typ
max
8.0
12
V
DD
V
DD
0.3V
DD
1.3
0.4V
DD
13
8
15
30
1.5
1.5
15
Unit
V
V
V
V
V
V
V
V
V
MHz
MHz
Vrms
Vrms
MHz
Input low-level voltage
Output voltage
Input frequency
Input amplitude
Required oscillating
frequency
10.24
10.24
Electrical Characteristics
at under allowable operating conditions
Parameter
Internal feedback resistance
Pull-down resistor
Symbol
Rf1
Rf2
RpdN
I
IH
1
I
IH
2
I
IH
3
I
IH
4
I
IL
1
I
IL
2
I
IL
3
I
IL
4
V
OH
1
V
OH
2
V
OL
1
V
OL
2
V
OL
3
V
OL
4
V
OL
5
V
OL
6
Output leakage current
High-level tristate leakage
current
Low-level tristate leakage
current
I
OFF
1
I
OFF
2
I
OFFH
I
OFFL
I
DD
1
Supply current
I
DD
2
Conditions
Pin XIN
Pin PIN
Pins KI1, KI2, KI3, KI4, TEST
Pins HOLD, TX V
I
= 12 V
Pin INIT V
I
= V
DD
Pin XIN V
I
= V
DD
Pin PIN V
I
= V
DD
Pins HOLD, TX V
I
= V
SS
Pin INIT V
I
= V
SS
Pin XIN V
I
= V
SS
Pin PIN V
I
= V
SS
Pins KO1, KO2, KO3 I
O
= 1 mA
Pin PD I
O
= 0.5 mA
Pins KO1, KO2, KO3 I
O
= 20 µA
Pin PD I
O
= 0.5 mA
Pin BEEP I
O
= 2 mA
Pins SA, SB, SC, SD, SE, SF, SG
I
O
= 20 mA
Pins D1, D2 I
O
= 5 mA
Pin UL I
O
= 10 mA
Pins SA, SB, SC, SD, SE, SF, SG, D1, D2
V
O
= 13 V
Pins UL, BEEP V
O
= 8 V
Pin PD V
O
= V
DD
Pin PD V
O
= V
SS
Normal mode
*1
(PLL operates)
Hold mode V
DD
= 3.2 V
*2
(memory backup)
V
DD
= 8.0 V
min
typ
1.0
500
50
max
Unit
MΩ
kΩ
kΩ
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
µA
µA
nA
nA
mA
µA
µA
30
Input high-level current
Input low-level current
Output high-level voltage
V
DD
–2.0
V
DD
–1.0
0.6
V
DD
–1.0
1.0
70
5.0
5.0
25
50
5.0
5.0
25
50
V
DD
–0.5
1.4
1.0
1.0
1.0
1.0
1.0
5.0
5.0
Output low-level voltage
0.01
0.01
5
10.0
10.0
10
5
15
*1: f
IN
2 = 20 MHz (PIN)
V
IN
2 = 0.15 Vrms
X’tal = 10.240 MHz
TX = HOLD = INIT = V
DD
Other inputs = V
SS
Other outputs = open
*2: HOLD = V
SS
TX = INIT = V
DD
Other inputs = V
SS
Other outputs = open
Note: Be careful that the dielectric strength of pins SA, SB, SC, SD, SE, SF, D1, D2, UL, BEEP are weak.
No. 3356-2/12
LC7185-8750
Package Dimensions
unit : mm
Pin Assignment
3061-DIP30S
[LC7185-8750]
SANYO : DIP30S (400 mil)
Block Diagram
No. 3356-3/12
LC7185-8750
Pin Descriptions
TX
HOLD
INIT
TEST
V
DD
, V
SS
1, V
SS
2
PIN
XIN, XOUT
UL
Transmit/receive select
Hold mode select
Initial input
Test point (input)
Power supply
Programmable divider input
Crystal oscillator input, output
(10.240 MHz)
Unlock detection signal output
PD
NC
SA to SG
D1, D2
KI1 to KI4
KO1 to KO3
BEEP
Charge pump output
NC pin
Segment driver (for display)
Digit output (for display)
Key inputs
Key scan outputs
Beep-tone control output
Key Matrix
CH9
CH19
PA
MODE 1/2
UP
DN
Emergency CH9 recall
Emergency CH19 recall
Public announcement display
Display Mode
CH up/scan
CH down/scan
ME
M1 to M5
UP/DN/ME/M1 to 5
CH9/CH19/PA
MODE 1/2
Station Memory Enable
Station Memory recall
Momentary SW
Slide SW
Diode
LED Display Configuration (Common anode/7 segment)
No. 3356-4/12
LC7185-8750
Pin Description
Pin Name
TX
HOLD
Pin No.
30
26
Type
.
.
.
.
.
.
.
.
.
Description
Transmit/receive select
TX = ‘‘0’’...Transmit, TX = ‘‘1’’...Receive
Hold mode select
HOLD = ‘‘0’’...Hold mode select
= ‘‘1’’...Normal mode select
Reset line
INIT = ‘‘0’’...Reset
Test point (input)
Tie to ground or leave floating
INIT
TEST
25
22
V
DD
24
Power supply (+)
Normal mode: 5.0 to 8.0 V
Hold mode:
^
3.2 V
Channel display LED driver ground
Programmable divider input
150 mVrms min
Hold mode: Programmable divider is disabled.
V
SS
2
PIN
21
23
XIN
XOUT
20
19
Crystal oscillator
Frequency: 10.24 MHz
Hold mode: Oscillator is disabled.
PD
27
.
.
.
V
SS
1
NC
UL
28
29
18
Charge pump output from the phase comparator. If the frequency of fV
(the signal obtained by dividing the PIN input by N) is higher than that of
fR (the reference signal), or if the phase of fV leads that of fR, positive
pulses are output on this pin. If the frequency is lower or the phase lags,
negative pulses are output on this pin. If they match, the pin goes to high
impedance.
fV > fR OR leading: Positive Pulses
fV < fR OR leading: Negative Pulses
fV = fR and phase muched: High impedance
.
.
.
.
Hold mode: High impedance
PLL circuit and controller ground
No-connection
Unlock detected output
Fixed to low level when unlocked, when changing channels, in PA mode,
or in hold mode.
Open: Locked
BEEP
17
Beep-tone control output
During station memory operation
During I/O on emergency channel
When changing channels
During reset
During hold mode recovery
Fixed to low level in hold mode
Segment drivers for the display
(Common anode/7 segments)
— Transistor: Off (50 ms cycle)
→
Open
SA to SG
1 to 7
.
.
D1
D2
8
9
Digit output (150 Hz) for the display
(common anode/7 segments)
Hold mode: Transistor goes off.
Continued on next page.
No. 3356-5/12
Microcontroller MCU
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