74LVCH1T45GF datasheet, PDF - EEWORLD Datasheet

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74LVCH1T45GF: DescriptionLVC/LCX/Z SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6; Categorysemiconductor logic; File Size256KB，30 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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74LVCH1T45GF Overview

LVC/LCX/Z SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6

74LVCH1T45GF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of ports	2
Number of terminals	6
Minimum operating temperature	-40 Cel
Maximum operating temperature	125 Cel
Rated supply voltage	1.5
Minimum supply/operating voltage	1.2 V
Maximum supply/operating voltage	5.5 V
Processing package description	1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, SON-6
each_compli	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	Active
Logic IC type	BUS TRANSCEIVER
series	LVC/LCX/Z
jesd_30_code	S-PDSO-N6
jesd_609_code	e3
moisture_sensitivity_level	1
Number of digits	1
Output characteristics	3-STATE
Output polarity	TRUE
Packaging Materials	PLASTIC/EPOXY
ckage_code	VSON
packaging shape	SQUARE
Package Size	SMALL OUTLINE, VERY THIN PROFILE
eak_reflow_temperature__cel_	260
propagation delay TPD	23.5 ns
qualification_status	COMMERCIAL
seated_height_max	0.5000 mm
surface mount	YES
Craftsmanship	CMOS
Temperature level	AUTOMOTIVE
terminal coating	TIN
Terminal form	NO LEAD
Terminal spacing	0.3500 mm
Terminal location	DUAL
ime_peak_reflow_temperature_max__s_	30
length	1 mm
width	1 mm

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74LVC1T45; 74LVCH1T45

Dual supply translating transceiver; 3-state

Rev. 02 — 19 January 2010

Product data sheet

1. General description

The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs

that enables bidirectional level translation. They feature one data input-output port (A and

B), a direction control input (DIR) and dual supply pins (V

CC(A)

and V

CC(B)

). Both V

CC(A)

and V

CC(B)

can be supplied at any voltage between 1.2 V and 5.5 V making the device

suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,

3.3 V and 5.0 V). Pins A and DIR are referenced to V

CC(A)

and pin B is referenced to

CC(B)

. A HIGH on DIR allows transmission from A to B and a LOW on DIR allows

transmission from B to A.

The devices are fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V

CC(A)

or V

CC(B)

are at

GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid

logic level.

2. Features

Wide supply voltage range:

CC(A)

: 1.2 V to 5.5 V

CC(B)

: 1.2 V to 5.5 V

High noise immunity

Complies with JEDEC standards:

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

ESD protection:

HBM JESD22-A114E Class 3A exceeds 4000 V

CDM JESD22-C101C exceeds 1000 V

Maximum data rates:

420 Mbps (3.3 V to 5.0 V translation)

210 Mbps (translate to 3.3 V))

140 Mbps (translate to 2.5 V)

75 Mbps (translate to 1.8 V)

60 Mbps (translate to 1.5 V)

Suspend mode

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