LOW SKEW, 1-TO-16, LVCMOS/LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
ICS8316
G
ENERAL
D
ESCRIPTION
The ICS8316 is a low skew, 1-to-16 LVCMOS/LVTTL
Fanout Buffer with 1.2V LVCMOS Outputs and a
HiPerClockS™
member of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The ICS8316 single
ended clock input accepts LVCMOS or LVTTL input
levels. The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines.
F
EATURES
•
Sixteen 1.2V LVCMOS / LVTTL outputs
•
LVCMOS / LVTTL clock input
•
Maximum output frequency: 150MHz
•
Output skew: 380ps (maximum)
•
Propagation delay: 4.6ns (maximum)
•
3.3V core/1.2V output operating supply mode
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Guaranteed output and part-to-par t skew character istics
along with the 1.2V output makes the ICS8316 ideal for high per-
formance, single ended applications that also require a limited
output voltage.
B
LOCK
D
IAGRAM
CLK
P
IN
A
SSIGNMENT
GND
GND
OED
V
DDO
QD3
QD2
QD1
QD0
4
QA0:QA3
V
DDO
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
V
DDO
QC0
QC1
QC2
QC3
GND
OEC
GND
OEA
4
QB0:QB3
QA0
QA1
QA2
OEB
4
QC0:QC3
QA3
GND
ICS8316
21
20
19
18
17
OEC
4
QD0:QD3
OEA
CLK
OED
9 10 11 12 13 14 15 16
V
DD
OEB
GND
QB3
QB2
QB1
QB0
V
DDO
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT
™
/ ICS
™
1-TO-16, 1.2V LVCMOS FANOUT BUFFER
1
ICS8316AK REV. B FEBRUARY 29, 2008
ICS8316
LOW SKEW, 1-TO-16, LVCMOS/LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 16, 24, 25
2, 3, 4, 5
6, 11, 17,
19, 30, 32
7
8
9
10
12, 13, 14, 15
18
20, 21, 22, 23
26, 27, 28, 29
Name
V
DDO
QA0, QA1, QA2, QA3
GND
OEA
CLK
V
DD
OEB
QB3, QB2, QB1, QB0
OEC
QC3, QC2, QC1, QC0
QD0, QD1, QD2, QD3
Power
Output
Power
Input
Input
Power
Input
Output
Input
Output
Output
Pullup
Pullup
Pullup
Type
Description
Output supply pins.
Bank A clock outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Bank A output enable pin. Controls enabling and disabling
of QA0:QA3 outputs. LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Power supply pin.
Bank B output enable pin. Controls enabling and disabling
of QB0:QB3 outputs. LVCMOS / LVTTL interface levels.
Bank B clock outputs. LVCMOS / LVTTL interface levels.
Bank C output enable pin. Controls enabling and disabling
of QC0:QC3 outputs. LVCMOS / LVTTL interface levels.
Bank C clock outputs. LVCMOS / LVTTL interface levels.
Bank D clock outputs. LVCMOS / LVTTL interface levels.
Bank D output enable pin. Controls enabling and disabling
31
OED
Input
Pullup
of QD0:QD3 outputs. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 1.2 ± 5%
8
Test Conditions
Minimum
Typical
4
V
DDO
= 1.26V
51
51
13
21
15
Maximum
Units
pF
pF
kΩ
kΩ
Ω
T
ABLE
3A. O
UTPUT
E
NABLE
Control Inputs
OE[A:D]
0
1
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Outputs
Qx0:Qx3
Hi-Z
Active
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE[A:D]
1
1
CLK
0
1
Outputs
Qx0:Qx3
LOW
HIGH
IDT
™
/ ICS
™
1-TO-16, 1.2V LVCMOS FANOUT BUFFER
2
ICS8316AK REV. B FEBRUARY 29, 2008
ICS8316
LOW SKEW, 1-TO-16, LVCMOS/LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
34.8°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V, V
DDO
= 1.2V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.14
Typical
3.3
1.2
Maximum
3.465
1.26
10
10
Units
V
V
µA
µA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK
OEA:OED
CLK
OEA:OED
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 1.2V ± 5%; NOTE 1
V
DDO
= 1.2V ± 5%; NOTE 1
-5
-150
V
DDO
* 0.7
V
DDO
* 0.3
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0. 8
150
5
Units
V
V
µA
µA
µA
µA
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagram.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.2V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 3
Bank Skew; NOTE 3, 4
Par t-to-Par t Skew; NOTE 3, 5
Output Rise Time
Output Duty Cycle
20% to 80%
Fout
≤
100MHz
350
47
2.3
3.45
Test Conditions
Minimum
Typical
Maximum Units
150
4.6
380
70
1.2
850
53
MHz
ns
ps
ps
ns
ps
%
t
sk(o)
t
sk(b)
t
sk(pp)
t
R
/t
F
odc
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
IDT
™
/ ICS
™
1-TO-16, 1.2V LVCMOS FANOUT BUFFER
3
ICS8316AK REV. B FEBRUARY 29, 2008
ICS8316
LOW SKEW, 1-TO-16, LVCMOS/LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2.7V±5%
0.6V±5%
V
DD
V
DDO
SCOPE
Qx
Qx
V
DDO
2
LVCMOS
GND
V
DDO
Qy
2
tsk(o)
-0.6V±5%
3.3V C
ORE
/1.2V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
Part 1
Qx
V
DDO
2
Qx0:Qx3
V
DDO
2
Part 2
Qy
V
DDO
Qx0:Qx3
tsk(b)
V
DDO
2
2
tsk(pp)
P
ART
-
TO
-P
ART
S
KEW
B
ANK
S
KEW
(
where x denotes outputs in the same bank
)
CLK
V
DD
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QD0:QD3
t
PW
t
V
DDO
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QD0:QD3
V
DDO
2
t
PD
PERIOD
odc =
t
PW
t
PERIOD
x 100%
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
LUSE
W
IDTH
/P
ERIOD
80%
20%
t
R
80%
20%
t
F
Clock
Outputs
O
UTPUT
R
ISE
/F
ALL
T
IME
IDT
™
/ ICS
™
1-TO-16, 1.2V LVCMOS FANOUT BUFFER
4
ICS8316AK REV. B FEBRUARY 29, 2008
ICS8316
LOW SKEW, 1-TO-16, LVCMOS/LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
A
PPLICATION
I
NFORMATION
R
ECOMMENDATIONS FOR
U
NUSED
I
NPUT AND
O
UTPUT
P
INS
I
NPUTS
:
O
UTPUTS
:
LVCMOS C
ONTROL
P
INS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVCMOS O
UTPUTS
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
VFQFN EPAD T
HERMAL
R
ELEASE
P
ATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 1.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE
THERMAL VIA
LAND PATTERN
(GROUND PAD)
PIN PAD
F
IGURE
1. P.C.A
SSEMBLY FOR
E
XPOSED
P
AD
T
HERMAL
R
ELEASE
P
ATH
–S
IDE
V
IEW
(D
RAWING NOT TO
S
CALE
)
IDT
™
/ ICS
™
1-TO-16, 1.2V LVCMOS FANOUT BUFFER
5
ICS8316AK REV. B FEBRUARY 29, 2008
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