or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
Introduction_01.4
Introduction
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For
maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-
DSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™
(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function
blocks to achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
LatticeECP/EC Family Data Sheet
Architecture
September 2012
Data Sheet
Architecture Overview
The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/
O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as
shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in
Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core volt-
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
There are some classic circuits in ADI experimental circuits. I would like to share the Howland current source circuit with you: (This circuit is in AN-843)...
1. Calibration steps: Control Panel-Pointer-Recalibrate 2. Read the calibrated reference value path: My Device-Windows-regedit [HKEY_LOCAL_MACHINE\HARDWARE\DEVICEMAP\TOUCH] "CalibrationData"="2074,199...
1. External interruption receives a frame of data, and after receiving it, the new data is displayed on the LED dot matrix. (Strangely, the data update is normal, but there are random dots during on-s...
In the power supply board of mobile portable electronic products, in addition to considering how to manage the battery power, there are often many issues to consider when selecting the control chip. T...
At present, the development of wireless power supply technology for electric vehicles (EVs) is becoming more and more active. In 2012, Volvo of Sweden established Volvo Technology Japan in Tokyo as...[Details]
With the rapid development of science and technology, especially the widespread application of digital technology and various ultra-large-scale integrated circuits, electronic equipment, especially...[Details]
1. Introduction
Since the 1980s, with the continuous development of automotive electronic technology, there are more and more electronic control units in automobiles, such as electronic fuel i...[Details]
Automotive applications are particularly sensitive to EMI events, which are unavoidable in a noisy electrical environment consisting of a central battery, bundled wiring harnesses, various inductiv...[Details]
introduction
In the discharge process of tokamak plasma physics, the study of rupture and sawtooth is of great significance. Rupture and sawtooth exist in most tokamaks. Rupture is a notew...[Details]
The Mobile Industry Processor Interface (MIPI) Alliance is an organization responsible for promoting the standardization of software and hardware in mobile devices. It has released the D-PHY specif...[Details]
In order to highlight the concept of "energy saving and environmental protection" of intelligent buildings, solar street lights are designed for intelligent communities. The inclination and capacit...[Details]
1 Introduction
Ultrasonic waves have strong directivity, slow energy consumption, and can propagate over long distances in a medium, so they are used for distance measurement. Ultrasonic detec...[Details]
Although it is relatively easy to check the stability of a simple amplifier at lower frequencies, it may be much more difficult to evaluate the stability of a more complex circuit. This artic...[Details]
introduction
MAX6636 is a multi-channel precision temperature monitor that can not only monitor local temperature, but also connect up to 6 diodes externally. Each channel has a programmable...[Details]
hint:
The number of speakers and their spacing limit the sound field of a portable stereo system.
Spatial audio attempts to artificially recreate the experience of listening to sounds i...[Details]
1 Basic Features
In computer control systems and various intelligent instruments and meters composed of single-chip microcomputers (or microprocessors), various external analog signals must be ...[Details]
0 Introduction
There are many types of sensors, and the working principles, measurement targets and measurement environments of different types of sensors vary greatly. The corresponding detection s...[Details]
1 What is an LED floodlight?
LED downlights are also called spotlights, projection lamps, and spotlights. They are mainly used for architectural decorative lighting and commercial space lighti...[Details]
ADI Reference Circuit
京公网安备 11010802033920号
EEWORLD
