EEWORLDEEWORLDEEWORLD

Part Number

Search

50011-5078L

Description
Board Connector, 78 Contact(s), 4 Row(s), Male, Straight, Press Fit Terminal
CategoryThe connector    The connector   
File Size432KB,7 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

50011-5078L Overview

Board Connector, 78 Contact(s), 4 Row(s), Male, Straight, Press Fit Terminal

50011-5078L Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Reach Compliance Codecompliant
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD FLASH (30) OVER PALLADIUM NICKEL
Contact completed and terminatedGOLD FLASH (30) OVER PALLADIUM NICKEL
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee4
MIL complianceNO
Manufacturer's serial number50011
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded4
OptionsGENERAL PURPOSE
Terminal pitch2.54 mm
Termination typePRESS FIT
Total number of contacts78
UL Flammability Code94V-0
Base Number Matches1
PDM: Rev:K
STATUS:
Released
Printed: May 13, 2011
.
How many timers does MPS430G2553 have?
I see in the documentation that 2553 has two timers, but why is there only the register definition of TIMER_A in the header file of the 430ware routine? Also, the official documentation says there are...
jishuaihu Microcontroller MCU
Has anyone used the Red Hurricane II FPGA development board? Help~
[size=5][color=red]The chip on the CY1C12 development board I have is the FPGA EP1C12Q240C8. Today I used a small program to try to light up the four seven-segment digital tubes. It uses dynamic displ...
zqzq501311 FPGA/CPLD
Windows CE6.0 USB keyboard and mouse
Hello everyone, when I am customizing the system, I want to add support for USB keyboard and mouse. May I ask which components, Reg files and BIB files I need to add?...
dragonkjl Embedded System
A few tips on XILINX FPGA design
Tips on XILINX FPGA design 1. Use a global clock buffer BUFG for the clock signal 2. Try to use only one clock edge to register data 3. Do not generate clocks internally except for the clocks generate...
cobble1 FPGA/CPLD
EE_FPGA V1.0 Debugging Progress (Updated on 2010.10.17)
front:Reverse:Current progress: 1. Minimum system operation 2. LED work 3. Key work 4. The USB to serial port driver is normal and the serial port works normallyThe pictures will be posted later, plea...
chenzhufly FPGA/CPLD
DesignStellaris: Bicycle ABS brake system based on LM3S9B96, source code download available
The innovative design of Stellaris that I want to share with netizens today is a bicycle ABS brake system. I hope you will like it.After TI acquired Luminary in 2009, it held another Stellaris Innovat...
Study_Stellaris Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 121  1243  1798  27  1740  3  26  37  1  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号