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LFE212E-7FN672C: DescriptionLatticeECP2/M Family Data Sheet; File Size2MB，386 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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LFE212E-7FN672C Overview

LatticeECP2/M Family Data Sheet

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LatticeECP2/M Family Data Sheet

DS1006 Version 03.3, August 2008

LatticeECP2/M Family Data Sheet

Architecture

August 2008

Data Sheet DS1006

Architecture Overview

Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains

SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

ﬂexibility, allowing complex designs to be implemented quickly and efﬁciently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated

18K fast memory blocks. Each sysMEM block can be conﬁgured in a variety of depths and widths of RAM or ROM.

In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels.

Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic.

Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The

functionality of the SERDES/PCS Quads can be controlled by memory cells set during device conﬁguration or by

registers that are addressable during device operation. The registers in every quad can be programmed by a soft

IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners

of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of

the device can be conﬁgured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support

to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory

interfaces including DDR2.

Other blocks provided include PLLs, DLLs and conﬁguration functions. The LatticeECP2/M architecture provides

two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family

member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom-

most EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of

the other EBR/DSP rows.

The conﬁguration block that supports features such as conﬁguration bit-stream decryption, transparent updates

and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in

the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and ﬁve, which

allows for serial or parallel device conﬁguration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP2/M devices use 1.2V as their core voltage.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1006

Architecture_01.9

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