Differential PECL Crystal Clock Oscillators
3HPF5761 Series
+3.3V “F” family
3HPF5761
features 0.4 ps typical phase jitter and
low phase noise (-132 dBc at 10 KHz for 155.520 MHz).
Differential PECL Outputs meet the requirements for
SONET, XDSL and other communication protocols.
General Specifications
Product Series
Frequency Range
Output Logic
Frequency Stability
vs Operating Temperature
Range
PECL Outputs
MERCURY
Since 1973
3HPF5761; “F” family characteristics. Tri-State on pad 1
38 MHz ~ 640 MHz.
Differential PECL 100 K square wave
Commercial “ C ”::
Industrial
“
I
”:
Stability Code
-10°C to +70°C
-40°C to +85°C
±25 ppm
A
D
±50 ppm
B
E
±100 ppm
C
F
Custom ±xx ppm
Cxx
Ixx
If custom, use “temperature range code + desired ppm stability” for the stability
code. Example: “C20” (±20 ppm over -10 to +70°C) or “I35”.
±3 ppm max.with ±10% supply voltage change
±2 ppm max.with ±10% Load change:
+3.3 V ± 10 %
2.275 V min.; 2.420 V max. Condition: 50 ohms to V
DD
-2V
1.490 V min..; 1.680 V max. Condition: 50 ohms to V
DD
-2V
38 MHz≤ fout
≤
100 MHz: 70 mA max.
100 MHz< fout
≤
320 MHz: 85 mA max
320 MHz< fout
≤
640 MHz: 95 mA max
50 ohms into V
CC
-2V or Thevenin equivalent (terminating resistors required on all
outputs).
fout < 150 MHz: 0.5 ns typical; 0.7 ns max.
150 MHz
≤
fout
≤
320 MHz: 0.4 ns. typical; 0.55 ns. max
f320 MHz < fout
≤
640 MHz: 0.3 ns. typical; 0.45 ns. max
Measured at 20%
↔
80% of the wave form.
50% ± 5% max. measured at 50% waveform
3HPF5761: Tri-State is on pad 1. Pad 2 is no connection.
3HPF5762: Tri-State is on pad 2. Pad 1 is no connection.
Differential PECL and complimentary PECL outputs.
Both outputs are disabled (high impedance) when pad No. 2 is taken
below 0.45＊Vcc referenced to ground (threshold). Oscillator is always
ON. Only buffer stage is disabled.
Disable current: 50 uA max. (at 0.0 V).
Disable time: 10 ns max.
At disabled mode, both outputs are enabled when pad No. 2 is taken
above 0.45＊Vcc referenced to ground (threshold).
Enable time: 10ns+one period of the output frequency max.
0.5 ps max. (12 KHz to 20 MHz integrated)
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
vs Supply Voltage Change
vs Load Change
Supply Voltage V
CC
Output Voltage HIGH “1”, V
OH
Output Voltage LOW “0”, V
OL
Current Consumption
Load
Rise Time (Tr) and
Fall Time (Tf)
Duty Cycle
No Connection
Tri-state
Function on
pad No. 1
Disable
Enable
Phase Jitter (RMS)
Offset
SSB Phase
Taiwan: TEL (886)-2-2406-2779, FAX (886)-2-2496-0769, e-mail: sales-tw@mercury-crystal.com
U.S.A.: TEL (1)-909-466-0427, FAX (1)-909-466-0762, e-mail:
sales-us@mercury-crystal.com
MERCURY
Page 1 of 4
Date: April 1, 2008
Rev. 1
MERCURY
www.mercury-crystal.com
Differential PECL Crystal Clock Oscillators
3HPF5761 Series
+3.3V “F” family
Noise (dBc/Hz)
77.760 MHz
106.250 MHz
155.520 MHz
311.020 MHz
622.080 MHz
77.760 MHz
106.250 MHz
155.520 MHz
311.020 MHz
622.080 MHz
-65
-66
-62
-59
-49
-96
-124
-96
-122
-92
-120
-85
-117
-84
-111
Period Jitter
(RMS)
2.5 ps typ; 4.0 ps max
3.0 ps typ; 5.0 ps max
3.0 ps typ; 5.0 ps max
3.0 ps typ; 5.0 ps max
6.0 ps typ; 8.0 ps max
5 m sec. max.
±3 ppm / year max.
PECL Outputs
-136
-132
-132
-126
-132
-128
-128
-125
-120
-118
Period Jitter
(peak-to-peak)
18 ps typ.; 30 ps max
20 ps typ.; 30 ps max
20 ps typ.; 30 ps max
25 ps typ.; 30 ps max
40 ps typ.; 50 ps max
MERCURY
Since 1973
-145
-149
-144
-150
-144
-150
-139
-148
-128
-138
Integrated Jitter RMS
(12 KHz ~20 MHz)
0.4 ps typ; 0.5 ps max.
0.4 ps typ; 0.5 ps max.
0.4 ps typ; 0.5 ps max.
0.4 ps typ; 0.5 ps max.
0.4 ps typ; 0.5 ps max.
Jitter
Start-up Time
Aging
Packaging
Contact Pad Surface Finish
(1)
179 mm reel; 16 mm tape, 8.0 mm pitch. 1000 pcs per reel.
Gold over nickel on ceramic substrate
Inclusive of 25°C tolerance, operating temperature range, ±10% input voltage variation, load change, aging at +25°C, shock and
vibration.
Absolute Maximum Rating
Permanent damage may be created if operate beyond limits specified
Supply Voltage V
DD
Input Voltage Vi
Input Voltage Vo
E S D Protection
Environmental Performance Specifications
Green Requirement
Moisture Sensitivity Level
Storage temp. range
Humidity
Hermetic seal
Solderability
Vibration
Shock
Part Number Format and Example:
Example:
3HPF5761A-155.520
Explanation:
+3.3V HPF576 series PECL output clock oscillator, 155.520 MHz, frequency stability is ±25 ppm over
0°C to +70°C, frequency deviation range is ±100 ppm minimum.
: customer to specify
3
HPF5761
—
A
—
155.520
: Voltage codes: “3” for +3.3 V; : HPF5761 product series. ‘H” for clock; “P” for PECL; “F”: for “F” family
performance.“576” for 5x7 mm SMD with 6 pads. ‘1” for Tri-State on pad 1.
: Frequency stability code: “A” ~ “F” or custom. See table above. : Frequency in MHz
RoHS Compliant and Pb (lead) free
Level 1
-55 to +125°C
85% RH, 85°C, 48 hours
Leak rate 2x10
-8
ATM-cm
3
/sec max.
MIL-STD-202F method 208E
MIL-STD-202F method 204, 35G, 50 to 2000 Hz
MIL-STD-202F method 213B, test condi. E, 1000GG ½ sine wave
+4.6 V D.C. max.
Vss-0.5V min.; V
DD
+0.5V max.
Vss-0.5V min.; V
DD
+0.5V max.
2 KV max. Human body model
MERCURY
Page 2 of 4
Date: April 1, 2008
Rev. 1
Differential PECL Crystal Clock Oscillators
3HPF5761 Series
+3.3V “F” family
3HPF5761 Package Dimensions and Recommended Pad Layout:
PECL Outputs
MERCURY
Since 1973
unit mm[inches]
[0.197± 0.006]
5.00± 0.15
MEC
[0.004]
0.1
1.8 max.
[0.071 max.]
1
2
3
3
2
1
0.7 [0.028]
5.08 [0.200]
typical
bottom view
1.5[0.059]
1.8[0.071]
Pad 1 Tri-state
Pad 4 PECL Output
Pad 2 No Connection Pad 5 PECL Output
Pad 3 Ground
Pad 6 Supply Voltage
2.0[0.079]
Top view
Rounded pad is pad No. 1
3HPF576 Recommended Solder Reflow Profile
5.08 [0.200]
Topside temperature of board to be 260°C min. and 270°C max.
Peak Temperature: 260°C max. and 10 sec. max.
Time within 5°C of actual peak: 20 to 40 sec. max.
Liquidus Temperature
Flux Activation
Temperature
260
250
240
Temperature ( °C)
200
150
100
50
Pre-heat 1
30
t
Ram
up a
x.
p
6°C p dow
Ram
ec ma
n
/se
s
20~40 sec.
c m at
°C /
3
ax.
Soaking temp: 140°C~225°C
Soaking time: 60~120 sec.
Reflow
Zone
Soaking Zone
30~60 sec.
Pre-heat 2
Cooling
R0
.7
3HPF5761
[0.050]
1.27
[0.275± 0.006]
7.00± 0.15
5
6
4
0.6[0.024]
2.54[0.100]
[0.055]
1.4
6
4
5
60
90
120 150 180
210 240 270 300 330
Time
(sec)
MERCURY
Page 4 of 4
Date: April 1, 2008
Rev. 1
FPGA/CPLD
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