PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
FEATURES
DDR SDRAM Data Rate = 200, 250,
266, and 333 Mbps
Package:
• 25mm x 25mm, Encapsulated
Plastic Ball Grid array (PBGA), 219
balls, 1.27mm pitch.
2.5V ±0.2V Core Power supply
2.5V ±0.2V I/O Power supply
(SSTL_2 compatible)
Differential Clock inputs (CLKx,
CLKx\)
Commands entered on each positive
CLKx edge
Internal pipelined double-data-
rate (DDR) Architecture; two data
accesses per clock cycle
Programmable Burst Length:
2, 4, or 8
Bidirectional data strobe (DQSLx,
DQsHx) per byte transmitted/
received with data
i.e. source-synchronous data capture
DQS edge-aligned with data for
READ; center-aligned with data for
WRITE
DLL to align DQx and DQSLx,
DQSHx transitions with CLKx
Four internal banks for concurrent
operation
One data mask per byte, IMOD con-
tains (10) bytes
Programmable IOL/IOH Option
Auto PRECHARGE option
Auto REFRESH and SELF
REFRESH Modes
Available in INDUSTRIAL,
EXTENDED and Mil-Temp ranges
Organized as 16M x 72/80
Weight: LOGIC Devices, Inc.
L9D112G80BG4 = 2.75 grams
typical
Benefits
53% SPACE savings vs. Monolithic,
TSOPII-66 solution
Reduced I/O routing (34%)
Reduced trace length providing
improved/reduced parasitic capaci-
tance
Impedance matched (60ohm) pack-
aging
High TCE organic laminate inter-
poser
Suitable for High Reliability applica-
tions
Upgradable to 32M x 72/80:
L9D125G80BG4
*Note: This integrated product and/or its specifications are subject to change without notice.
Latest document should be retrieved from LDI prior to your design consideration.
MONOLITHIC SOLUTION
O
P
T
I
O
N
S
AREA
I/O
11.9
11.9
11.9
11.9
11.9
IMOD SOLUTION
S
A
V
I
N
G
S
25mm
25mm
22.3
5 X 265mm = 1328mm PLUS
5 X 66 pins = 320 pins total
625mm
219 Balls/Locations
53%
34%
LOGIC Devices Incorporated
www.logicdevices.com
1
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
L9D112G80BG4, DDR1 SIGNAL LOCATION DIAGRAM
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ1
DQ3
DQ6
DQ7
CAS0\
CS0\
VSS
VSS
CLK3\
NC
DQ56
DQ57
DQ60
DQ62
VSS
2
DQ0
DQ2
DQ4
DQ5
DQML0
WE0\
RAS0\
VSS
VSS
CKE3
CLK3
DQMH3
DQ58
DQ59
DQ61
DQ63
3
DQ14
DQ12
DQ10
DQ8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ55
DQ53
DQ51
DQ49
4
DQ15
DQ13
DQ11
DQ9
5
VSS
VSS
VCC
VCCQ
6
VSS
VSS
VCC
VCCQ
7
A9
A0
A2
A12
8
A10
A7
A5
RFU
BA0
9
A11
A6
A4
RFU
BA1
10
A8
A1
A3
RFU
11
VCCQ
VCC
VSS
VSS
12
VCCQ
VCC
VSS
VSS
Vref
RAS1\
CAS1\
VCC
VCC
CLK2\
DQSL2
13
DQ16
DQ18
DQ20
DQ22
DQML1
WE1\
CS1\
VSS
VSS
CKE2
CLK2
DQMH2
DQ41
DQ43
DQ45
DQ47
14
DQ17
DQ19
DQ21
DQ23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ40
DQ42
DQ44
DQ46
15
DQ31
DQ29
DQ27
DQ26
NC
DQMH1
CLK1\
VCCQ
VCCQ
RAS2\
WE2\
DQML2
DQ37
DQ36
DQ34
DQ32
16
VSS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
VCC
VCC
CS2\
CAS2\
DQ39
DQ38
DQ35
DQ33
VCC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQMH0 DQSH3 DQSL0 DQSH0
CLK0
CKE0
VCCQ
VCCQ
CS3\
CAS3\
WE3\
DQ54
DQ52
DQ50
DQ48
DQSL3
CLK0\
VSS
VSS
DQSL4
RAS3\
DQML3
DQSH4
VSS
VCC
VCCQ
CKE4
CLK4\
VSS
VCC
VCCQ
DQMH4
DQ73
DQ75
DQ77
DQ79
DQSL1 DQSH1
CLK4
DQ72
DQ74
DQ76
DQ78
CAS4\
DQ71
DQ69
DQ67
DQ65
WE4\
DQ70
DQ68
DQ66
DQ64
RAS4\
CS4\
DQML4 DQSH2
VCC
VSS
VSS
VCC
VSS
VSS
1
2
3
VSS
Data IO
4
5
6
7
8
9
10
11
12
13
14
15
Address
16
V + (Core Power)
CNTRL
V + (I/O Power)
NC
UNPOPULATED
Level REF
LOGIC Devices Incorporated
www.logicdevices.com
2
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
F
unctional
B
lock
D
iagram
V
CCQ
V
CC
V
Ref
V
SS
A
0-
A
12,
BA
0-1
A, BA
V
SS
V
Ref
V
CC
V
CCQ
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
CS
0
\
RAS
0
\
CAS
0
\
CKE
0
CLK
0
CLK
0
\
WE
0
\
DQML
0
DQMH
0
DQSL
0
DQSH
0
D0
A, BA
V
SS
V
Ref
V
CC
V
CCQ
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
DQ
16
•
•
•
DQ
23
DQ
24
•
•
•
DQ
31
CS
1
\
RAS
1
\
CAS
1
\
CKE
1
CLK
1
CLK
1
\
WE
1
\
DQML
1
DQMH
1
DQSL
1
DQSH
1
D1
A, BA
V
SS
V
Ref
V
CC
V
CCQ
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
DQ
32
•
•
•
DQ
39
DQ
40
•
•
•
DQ
47
CS
2
\
RAS
2
\
CAS
2
\
CKE
2
CLK
2
CLK
2
\
WE
2
\
DQML
2
DQMH
2
DQSL
2
DQSH
2
D2
A, BA
V
SS
V
Ref
V
CC
V
CCQ
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
DQ
48
•
•
•
DQ
55
DQ
56
•
•
•
DQ
63
CS
3
\
RAS
3
\
CAS
3
\
CKE
3
CLK
3
CLK
3
\
WE
3
\
DQML
3
DQMH
3
DQSL
3
DQSH
3
D3
A, BA
V
SS
V
Ref
V
CC
V
CCQ
DQ
0
•
•
•
DQ
7
DQ
8
•
•
•
DQ
15
DQ
64
•
•
•
DQ
71
DQ
72
•
•
•
DQ
79
CS
4
\
RAS
4
\
CAS
4
\
CKE
4
CLK
4
CLK
4
\
WE
4
\
DQML
4
DQMH
4
DQSL
4
DQSH
4
D4
LOGIC Devices Incorporated
www.logicdevices.com
3
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
P
in
/B
all
l
ocations
/D
eFinitions anD
F
unctional
D
escriPtion
BGA Locations
F4, F16, G5, G15, K1,
K12, L2, L13, N6, M8
Symbol
Type
Description
CK
X
,CK
X
\ CNTL. Input
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CKx and negative edge of CKx\. Output data
(DQ’s and DQS) is referenced to the crossings of the differential clock inputs.
G4, G16, K2, K13, M6
CKE
x
CNTL. Input
Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock
input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous
for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for
SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout
READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers
are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS
LOW level after V
CC
is applied.
G1, G13, K4, K16, M12
CS
X
\
CNTL. Input
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) integrated
words. All commands are masked (registered) HIGH with CSx\ driven true. CSx\ provides for
external word/bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
F12, G2, K15, L5, M11
F1, G12, L4, L16, M9
F2, F13, L15, M4, M10
E2, E4, E13, F15, M2,
RAS
X
\
CAS
X
\
WE
X
\
DQML
X
,
CNTL. Input
Row Address Strobe: Command input along with CASx\ and WEx\
CNTL. Input
Column Address Strobe: Command input along with RASx\ and WEx\
CNTL. Input
WRITE (word): Command input along with CASx\ and RASx\
CNTL. Input
Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked
when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both
edges of DQSL/Hx.
M5, M7, M13, M15, N11
DQMH
X
E5, E6, E7, E10, E11,
F5, K5, L12, N5, N12
E12
DQSL
X
,
DQSH
X
Vref
Level REF
Input
Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned
with READ data, centered in WRITE data operations.
Reference Voltage
Address input: Provide the ROW address for ACTIVE commands and the COLUMN address
and AUTO PRE-CHARGE bit (A
10
) for READ/WRITE commands to select one location out of
the total array within a selected bank A
10
sampled during a PRE-CHARGE command deter-
mines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also
provide the OP-CODE during a MODE REGISTER SET command.
A7, A8, A9, A10, B7, B8,
A
0
-A
12
B9, B10, C7, C8, C9,
C10, D7
E8, E9
BA
0
, BA
1
Input
Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE
command.
LOGIC Devices Incorporated
www.logicdevices.com
4
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
P
in
/B
all
l
ocations
/D
eFinitions anD
F
unctional
D
escriPtion
c
ontinueD
BGA Locations
D8, D9, D10
A2, A3, A4, A13, A14,
A15, B1, B2, B3, B4,
B13, B14, B15, B16, C1,
C2, C3, C4, C13, C14,
C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1,
N2, N3, N4, N7, N8, N9,
N10, N13, N14, N15,
N16, P1, P2, P3, P4, P7,
P8, P9, P10, P13, P14,
P15, P16, R1, R2, R3,
R4, R7, R8, R9, R10,
R13, R14, R15, R16, T2,
T3, T4, T7, T8, T9, T10,
T13, T14, T15
B11, B12, C5, C6, E3,
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3, M3,
P11, P12, R5, R6, T16
A11, A12, D5, D6, H4,
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H5, H13, H14, J1, J2, J5,
J13, J14, K14, L14, M14,
P5, P6, R11, R12, T1,
T11, T12
V
SS
Supply
Ground (Digital)
V
CCQ
Supply
I/O Power
V
CC
Supply
Core Power
Symbol
RFU
Type
Input
Description
Reserved Future Use: Pins reserved for future Address and Bank Select inputs
DQ
0
-DQ
79
Input/Output
Data I/O
LOGIC Devices Incorporated
www.logicdevices.com
5
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
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