51766-10114400A0 datasheet, PDF

51766-10114400A0: DescriptionBoard Connector, 145 Contact(s), 4 Row(s), Female, Right Angle, Solder Terminal, Locking, Receptacle; CategoryThe connector The connector; File Size220KB，3 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

51766-10114400A0 Overview

Board Connector, 145 Contact(s), 4 Row(s), Female, Right Angle, Solder Terminal, Locking, Receptacle

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	TERMINAL PITCH FOR POWER CONTACTS: 6.35 MM
body width	0.448 inch
subject depth	0.82 inch
body length	3.94 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	NOT SPECIFIED
Contact point gender	FEMALE
Contact material	COPPER ALLOY
Contact resistance	20 mΩ
Contact style	HYBRID
DIN compliance	NO
Dielectric withstand voltage	2500VDC V
Durability	200 Cycles
Filter function	NO
IEC compliance	NO
maximum insertion force	6.95 N
Insulation resistance	500000000 Ω
insulator material	GLASS FILLED THERMOPLASTIC
MIL compliance	NO
Manufacturer's serial number	51766
Mixed contacts	YES
Installation option 1	LOCKING
Installation method	RIGHT ANGLE
Installation type	BOARD
Number of connectors	ONE
Number of rows loaded	4
Maximum operating temperature	105 °C
Minimum operating temperature	-20 °C
Options	GENERAL PURPOSE
Rated current (signal)	3 A
Guideline	UL
reliability	COMMERCIAL
Terminal length	0.135 inch
Terminal pitch	2.54 mm
Termination type	SOLDER
Total number of contacts	145
UL Flammability Code	94V-0
Base Number Matches	1

PDM: Rev:N

STATUS:

Released

Printed: Dec 20, 2010

Analog Electronics Course Selection Test: Watch the courses on the course list...; amperhong TI Technology Forum

About SPI mode setting: For SPI communication, there are only four pins: MOSI, MISO, CS, and CLK. SPI has four modes. So how do you set the various modes when using SPI? There are no clock polarity and phase pins?...; shijizai 51mcu

[FPGA Design Tips] Several concepts about FPGA clocks: delay, intermediate state and speed: InWhen the delay of data transfer between registers exceeds one clock cycle, the downstream register cannot sample the upstream data given in the current clock cycle in the next clock cycle, and an er...; eeleader FPGA/CPLD

Is there anyone who has ported the FLASH player to WINCE?: As the title says, if anyone has this question, please contact QQ: 414858335...; eddy326 Embedded System

Summary of works participating in the "Willful DIY" activity: [font=微软雅黑][size=3]This post is a collection of works participating in the "任性DIY" event. If you haven't participated in the event yet, hurry up and join us! [/size][/font][font=微软雅黑][size=3] [/size][...; eric_wang DIY/Open Source Hardware

[Sipeed LicheeRV 86 Panel Review] 14. lvgl displays images and local time: [i=s]This post was last edited by sonicfirr on 2022-4-25 21:03[/i]This article records the process of using the lvgl framework to display pictures, and also obtains the local time of the system and di...; sonicfirr Domestic Chip Exchange

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components