IMP51 11
5
D
ATA
C
OMMUNICATIONS
9-Line SCSI Terminator
Key Features
x
x
x
x
x
x
x
x
x
x
x
x
x
Ultra-Fast response for Fast-20 SCSI applications
35MHz channel bandwidth
3.3V operation
Less than 3pF output capacitance
375µA Sleep-mode current
Thermally self limiting
No external compensation capacitors
Implements 8-bit or 16-bit (wide) applications
Compatible with active negation drivers
(60mA/channel)
Compatible with passive and Active terminations
Approved for use with SCSI 1, 2, 3 and UltraSCSI
Hot swap compatible
Pin-for-pin compatible with DS21S07A/2105
– 35MHz Channel Bandwidth
The IMP5115 SCSI terminator is part of IMP's family of high-perfor-
mance, adaptive, non-linear mode SCSI products, which are designed to
deliver true UltraSCSI performance in SCSI applications. The low voltage
BiCMOS architecture employed in its design offers performance superior
to older linear passive and active techniques. IMP's SCSI termination
architecture employs high-speed adaptive elements for each channel,
thereby providing the fastest response possible — typically 35MHz,
which is 100 times faster than the older linear regulator/terminator
approach used by other manufacturers. Products using this older linear
regulator approach have bandwidths which are dominated by the output
capacitor and which are limited to 500KHz (see further discussion in the
Functional Description section). This new architecture also eliminates the
output compensation capacitor required in earlier terminator designs.
Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond —
providing the highest performance alternative available today.
Another key improvement offered by the IMP5115 lies in its ability to
insure reliable, error-free communications even in systems which do not
adhere to recommended SCSI hardware design guidelines, such as the
use of improper cable lengths and impedances. Frequently, this situation
is not controlled by the peripheral or host designer and, when problems
occur, they are the first to be made aware of the problem. The IMP5115
architecture is much more tolerant of marginal system integrations.
Recognizing the needs of portable and configurable peripherals, the
IMP5115 has a TTL compatible sleep/disable mode. Quiescent current
is typically 375µA in this mode, while the output capacitance is also
less than 3pF. The obvious advantage of extended battery life for
portable systems is inherent in the product's sleep-mode feature.
Additionally, the disable function permits factory-floor or production-
line configurability, reducing inventory and product-line
diversity costs. Field configurability can also be accom-
plished without physically removing components which,
often times results in field returns due to mishandling.
Reduced component count is also inherent in the IMP5115
architecture. Traditional termination techniques require
large stabilization and transient protection capacitors of up
to 20µF in value and size. The IMP5115 architecture does
not require these components, allowing all the cost savings
associated with inventory, board space, assembly, reliability,
and component costs.
Block Diagrams
Term Power
Thermal
Limiting
Circuit
Current
Biasing
Circuit
24mA Current
Limiting Circuit
DATA OUTPUT
PIN DB (0)
2.85V
DISABLE PIN
–
1 of 9 Channels
+
1.4V
5115_01.eps
© 2000 IMP, Inc.
Data Communications
1
IMP51 11
5
Pin Configuration
SO-16
TERM POWER
D0
D1
D2
D3
D4
NC
GND
1
2
3
4
5
6
7
8
D Package
IMP5115
16 DISABLE
15 NC
14 D8
13 D7
12 D6
11 D5
10 NC
9
NC
5115__02.eps
SOWB-16
TERM POWER
D0
D1
D2
D3
D4
NC
GND
1
2
3
4
5
6
7
8
DW Package
IMP5115
16 DISABLE
15 NC
14 NC
13 D8
12 D7
11 D6
10 D5
9
NC
5115__02a.eps
TSSOP-20
TERM POWER
HEAT SINK/GND
D0
D1
D2
D3
D4
HEAT SINK/GND
NC
1
2
3
4
5
6
7
8
9
IMP5115
20 DISABLE
19 NC
18 HEAT SINK/GND
17 NC
16 D8
15 D7
14 D6
13 D5
12 HEAT SINK/GND
11 NC
PWP Package
5115_02b.eps
GND 10
Ordering Information
Part Number
IMP5115CD
IMP5115CDT
IMP5115CDW
IMP5115CDWT
IMP5115CPWP
IMP5115CPWPT
Temperature Range
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
Package
16-pin Plastic SO
Tape and Reel, 16-pin Plastic SO
16-pin Plastic SOWB
Tape and Reel, 16-pin Plastic SOWB
20-pin Plastic TSSOP
Tape and Reel, 20-pin Plastic TSSOP
5115_t01.at3
Absolute Maximum Ratings
1
Continuous Termination Voltage . . . . . . . . . . . 10V
Continuous Output Voltage Range . . . . . . . . 0V to 5.5V
Continuous Disable Voltage Range . . . . . . . . 0V to 5.5V
Operating Junction Temperature . . . . . . . . . . 0°C to 125°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
D Package:
Thermal Resistance Junction-to-Ambient,
θ
JA
. . . . . . 120°C/W
DW Package:
Thermal Resistance Junction-to-Ambient,
θ
JA
. . . . . . 95°C/W
PWP Package:
Thermal Resistance Junction-to-Ambient,
θ
JA
. . . . . . 139°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JA
).
The
θ
JA
numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
2
408-432-9100/www.impweb.com
© 2000 IMP, Inc.
IMP51 11
5
Recommended Operating Conditions
2
Parameter
TermPwr Voltage
High Level Enable Input Voltage
Low Level Disable Input Voltage
Operating Junction Temperature Range
Symbol
V
TERM
V
IH
V
IL
Min
4.0
2
0
0
Typ
Max
5.5
V
TERM
0.8
125
Units
V
V
V
°C
5115_t02.eps
Note:
2. Recommended operating conditions indicate the range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of T
A
=
25°C. TermPwr = 4.75V. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage
TermPwr Supply Current
Symbol Conditions
V
OUT
I
CC
All data lines = Open
All data lines = 0.5V
Disable Pin < 0.8V
Min
2.65
Typ
2.85
6
215
375
Max
9
225
Units
V
mA
µA
Output Current
Disable Input Current
I
OUT
I
IN
V
OUT
= 0.5V
Disable Pin = 4.75V
Disable Pin = 0V
–21
–23
10
–90
10
3
35
–24
mA
nA
µA
nA
pF
MH z
mA
5115_t03.eps
Output Leakage Current
Capacitance in Disable Mode
Channel Bandwidth
Termination Sink Current, per Channel
I
OL
C
OUT
BW
I
SINK
Disable Pin < 0.8V, V
O
= 0.5V
V
OUT
= 0V, Frequency = 1MHz
V
OUT
= 4V
60
© 2000 IMP, Inc.
Data Communications
3
IMP51 11
5
Application Information
Figure 1. Receiving Waveform – 20MHz
Figure 2. Driving Waveform – 20MHz
Receiver
1 Meter, AWG 28
IMP5115
Driver
IMP5115
5115_03.eps
Figure 3.
IMP5115 Maximizes Line Current
Cable transmission theory suggests to optimize signal speed and
quality, the termination should act both as an ideal voltage refer-
ence when the line is released (deasserted) and as an ideal
current source when the line is active (asserted). Common active
terminators which consist of linear regulators in series with resis-
tors (typically 110Ω) are a compromise. With coventional linear
terminators as the line voltage increases the amount of current
decreases linearly by the equation;
Acting as a near ideal line terminator, the IMP5115 closely repro-
duces the optimum case when the device is enabled. To enable the
device the Disable pin must be driven LOW. When enabled,
quiescent current is 6mA and the device will respond to line
demands by delivering 24mA on assertion and by imposing 2.85V
on de-assertion.
Disable/Sleep Mode
Disable mode places the device in a sleep state, where quiescent
current typically 375µA. When disabled, all outputs are in a high
impedance state. Sleep mode can be used for power conservation
or to remove the terminator from the SCSI chain.
An additional feature of the IMP5115 are their compatibility with
active negation drivers.
(
V
REF
−
V
LINE
)
=
I.
R
The IMP5115, with its unique new architecture, applies the maxi-
mum amount of current regardless of line voltage until the
termination high threshold (2.85V) is reached.
Table 1. Power Up/ Power Down Function Table
Disable
H
L
Open
Outputs
Enabled
Disabled/High Impedance
Enabled
Quiescent Current
6mA
375
µA
6mA
5115_t04.eps
4
408-432-9100/www.impweb.com
© 2000 IMP, Inc.
IMP51 11
5
Package Dimensions
SO (16-Pin)
Inches
Min
A
A1
B
C
D
E
M
A
C
e
B
A1
L
16-Pin (SO).eps
Millimeters
Max
SO (16-Pin)*
0.069
0.010
0.018
0.010
0.394
0.158
0.244
0.030
0.104
0.012
0.018
0.013
0.420
0.305
0.419
0.035
0.078
0.015
0.008
0.311
0.212
Min
1.35
0.10
0.35
0.19
9.78
3.81
5.79
0.51
2.35
0.10
0.25
0.23
—
7.49
10.26
0.64
1.73
0.25
0.13
7.70
5.20
1.27 BSC
0.05
1.63
0.65
0°
7.65
Max
1.75
0.25
0.46
0.25
10.01
4.01
1.27 BSC
6.20
0.77
2.65
0.30
0.46
0.32
10.67
7.75
1.27 BSC
10.65
0.89
1.99
0.8
0.22
7.90
5.38
0.21
1.83
0.95
8°
7.90
5115_t05.at3
E
H
0.053
0.004
0.014
0.007
0.385
0.150
0.228
0.020
0.093
0.004
0.010
0.009
—
0.295
0.404
0.025
0.068
0.009
0.005
0.303
0.205
D
e
H
L
A
A1
B
C
D
E
e
H
L
A
B
C
D
E
F
0.050 BSC
SOWB (16-Pin)
SOWB (16-Pin)
0.050 BSC
E
H
TSSOP (20-Pin)
D
M
A
C
e
B
A1
L
16-Pin (SOWB).eps
0.025 BSC
TSSOP (20-Pin)
G
0.002
0.008
H
0.064
0.072
L
0.025
0.037
M
0°
8°
P
0.301
0.311
* JEDEC Drawing MS-012AC
E
P
1 2 3
D
F
A H
SEATING PLANE B
G
L
E
M
C
20-Pin (TSSOP).eps
© 2000 IMP, Inc.
Data Communications
5
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