LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-
TO-LVDS, LVPECL FANOUT BUFFER
ICS854S204I
G
ENERAL
D
ESCRIPTION
The ICS854S204I is a low skew, high performance
dual, programmable 1-to-2 Differential-to-LVDS,
HiPerClockS™
LVPECL Fanout Buffer and a member of the
HiPerClock S™ family of High Performance Clock
Solutions from IDT. The PCLKx, nPCLKx pairs can
accept most standard differential input levels. With the selection of
SEL_OUT signal, outputs can be selected be to either LVDS or
LVPECL levels. The ICS854S204I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed out-
put and bank skew characteristics make the ICS854S204I
ideal for those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
•
Two programmable differential LVDS or LVPECL output banks
•
Two differential clock input pairs
•
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
•
Maximum output frequency: 3GHz
•
Translates any single ended input signal to LVDS levels
with resistor bias on nPCLKx inputs
•
Output skew: 15ps (maximum)
•
Bank skew: 15ps (maximum)
•
Propagation delay: 500ps (maximum)
•
Additive phase jitter, RMS: 0.15ps (typical)
•
Full 3.3V or 2.5V power supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
P
OWER
S
UPPLY
C
ONFIGURATION
T
ABLE
3.3V Operation
2.5V Operation
V
DD
= 3.3V
V
TAP
= nc
V
DD
= 2.5V
V
TAP
= 2.5V
SEL_OUT F
UNCTION
T
ABLE
SEL_OUT
0
1
Output Level
LVDS
LVPECL
B
LOCK
D
IAGRAM
V
TAP
SEL_OUT
Pulldown
PCLKA
Pulldown
nPCLKA
Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
P
IN
A
SSIGNMENT
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
V
TAP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nPCLKB
PCLKB
QB0
nQB0
QB1
nQB1
V
DD
SEL_OUT
nPCLKB
PCLKB
Pulldown
Pullup
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
IDT
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
1
ICS854S204BGI REV. A JUNE 4, 2008
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5, 6
7
8
9
10
11, 12
13, 14
15
16
Name
PCLKA
nPCLKA
QA0, nQA0
QA1, nQA1
V
TAP
GND
SEL_OUT
V
DD
nQB1, QB1
nQB0, QB0
PCLKB
nPCLKB
Input
Input
Output
Output
Power
Power
Input
Power
Output
Output
Input
Input
Pullup
Pulldown
Type
Pullup
Description
Inver ting differential clock input.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Power supply pin. Tie to V
DD
for 2.5V operation.
For 3.3V operation, do not connect.
Power supply ground.
Selects between LVDS or LVPECL outputs.
Power supply pin.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
PCLKA or
PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA or
nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA0, QA1,
nQA0, nQA1,
QB0, QB1
nQB0, nQB1
HIGH
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
2
ICS854S204BGI REV. A JUNE 4, 2008
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
4.6V
-0.5V to V
DD
+ 0.5 V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
10mA
15mA
Package Thermal Impedance,
θ
JA
92°C/W (0 mps)
Storage Temperature, T
STG
(Junction-to-Ambient)
-65°C to 150°C
T
ABLE
4A. LVDS P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
120
Units
V
mA
T
ABLE
4B. LVDS P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
TAP
I
DD
I
TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
115
5
Units
V
V
mA
mA
T
ABLE
4C. LVPECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
66
Units
V
mA
T
ABLE
4D. LVPECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
TAP
I
DD
I
TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
60
5
Units
V
V
mA
mA
IDT
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
3
ICS854S204BGI REV. A JUNE 4, 2008
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
T
ABLE
4E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL_OUT
SEL_OUT
Test Conditions
V
DD
= 3.3V
V
DD
= 2.625V
V
DD
= 3.3V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
T
ABLE
4F. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
PCLKA,
PCLKB
I
IH
Input High Current
nPCLKA,
nPCLKB
PCLKA,
PCLKB
I
IL
Input Low Current
nPCLKA,
nPCLKB
Test Conditions
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
Minimum
Typical
Maximum
150
10
-10
-150
0.15
GND + 0.5
1. 3
V
DD
- 0.85
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
V
PP
T
ABLE
4G. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
∆
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
1.11
1.25
Minimum
247
Typical
350
Maximum
45 4
50
1.38
50
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4H. LVDS DC C
HARACTERISTICS
,
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
∆
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
1.08
1.21
Minimum
247
Typical
350
Maximum
45 4
50
1.34
50
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
IDT
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
4
ICS854S204BGI REV. A JUNE 4, 2008
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
T
ABLE
4I. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
V
DD
- 1.3
V
DD
- 2.0
0.6
Typical
Maximum
V
DD
- 0.8
V
DD
- 1.6
0.9
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DD
- 2V.
T
ABLE
4J. LVPECL DC C
HARACTERISTICS
,
V
DD
= V
TAP
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
V
DD
- 1.3
V
DD
- 2.0
0.6
Typical
Maximum
V
DD
- 0.8
V
DD
- 1.55
0.9
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DD
- 2V.
T
ABLE
5A. LVDS AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
100MHz, Integration Range:
12kHz – 20MHz
20% to 80%
Test Conditions
Minimum
Typical
Maximum
3
500
15
15
0.15
100
200
Units
GHz
ps
ps
ps
ps
ps
%
t
PD
t
sk(o)
t
sk(b)
t
jit
t
R
/ t
F
odc
Output Duty Cycle
49
51
All parameters measured at 550MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. LVDS AC C
HARACTERISTICS
,
V
DD
= V
TAP
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
100MHz, Integration Range:
12kHz – 20MHz
20% to 80%
Test Conditions
Minimum
Typical
Maximum
3
500
15
15
0.13
100
49
200
51
Units
GHz
ps
ps
ps
ps
ps
%
t
PD
t
sk(o)
t
sk(b)
t
jit
t
R
/ t
F
odc
Output Duty Cycle
For NOTES, see Table 5A above.
IDT
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
5
ICS854S204BGI REV. A JUNE 4, 2008
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