FemtoClocks–Crystal-TO-LVDS
Frequency Synthesizer
844002-01
DATA SHEET
Description
The 844002-01 is a 2 output LVDS Synthesizer optimized to
generate Ethernet reference clock frequencies. Using a 25MHz,
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz and 62.5MHz. The 844002-01 uses IDT’s
3
rd
generation low phase noise VCO technology and can achieve
<1ps typical rms phase jitter, easily meeting Ethernet jitter
requirements. The 844002-01 is packaged in a small 20-pin
TSSOP package.
Features
•
•
•
•
•
•
•
•
Two differential LVDS outputs
Selectable crystal oscillator interface or
single-ended LVCMOS/LVTTL input
Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
VCO range: 560MHz – 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.41ps (typical)
Full 3.3V and 2.5V supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
F_SEL[1:0]
Pulldown
PLL_SEL
Pulldown
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
2
Q0
1
Q0
nc
V
DDO
Q0
Q0
MR
PLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
Q1
GND
nc
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
REF_CLK
Pulldown
25MHz
1
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pulldown
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
0
Q1
Q1
M = 25 (fixed)
MR
Pulldown
844002-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
844002-01 Rev A 6/9/15
1
©2015 Integrated Device Technology, Inc.
844002-01 DATA SHEET
Table 1. Pin Descriptions
Number
1, 7
2, 20
3, 4
Name
nc
V
DDO
Q0, Q0
Power
Output
Type
Unused
Description
No connect.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs Qx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown
Pulldown
Non-inverting differential clock input.
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
No connect.
Power supply ground.
Differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
6
8
9,
11
10
12,
13
14
15
16
17
18, 19
PLL_SEL
V
DDA
FSEL0,
F_SEL1
V
DD
XTAL_OUT
,
XTAL_IN
REF_CLK
XTAL_SEL
nc
GND
Q1, Q1
Input
Power
Input
Power
Input
Input
Input
Unused
Power
Output
Pulldown
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
2
Rev A 6/9/15
844002-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.13
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
105
13
110
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.12
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
98
12
98
Units
V
V
V
mA
mA
mA
Rev A 6/9/15
3
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844002-01 DATA SHEET
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
2.625V
3.465V
V
IL
Input Low Voltage
2.625V
Input High Current
REF_CLK, MR,
FSEL0, FSEL1,
PLL_SEL, XTAL_SEL
REF_CLK, MR,
FSEL0, FSEL1,
PLL_SEL, XTAL_SEL
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-0.3
0.7
150
V
µA
1.7
-0.3
Test Conditions
3.465V
Minimum
2
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
Units
V
V
V
I
IH
I
IL
Input Low Current
-5
µA
Table 3D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.3
Test Conditions
Minimum
300
40
1.5
50
1.7
Typical
Maximum
600
Units
mV
mV
V
mV
Table 3E. LVDS DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
0.7
Test Conditions
Minimum
240
40
1.1
50
1.5
Typical
Maximum
550
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
22.4
Test Conditions
Minimum
Typical
Fundamental
25
27.2
50
7
1
MHz
Maximum
Units
pF
mW
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
4
Rev A 6/9/15
844002-01 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Parameter Symbol
f
OUT
tsk(o)
tjit(Ø)
Output Frequency
Output Skew; NOTE 1, 2
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz)
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
250
48
Test Conditions
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
Minimum
140
112
56
5
0.41
0.44
0.47
550
52
Typical
Maximum
170
136
68
20
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Parameter Symbol
f
OUT
tsk(o)
tjit(Ø)
Output Frequency
Output Skew; NOTE 1, 2
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz)
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
250
48
Test Conditions
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
Minimum
140
112
56
5
0.41
0.44
0.47
550
52
Typical
Maximum
170
136
68
20
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Rev A 6/9/15
5
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
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