HANBit
HMN12816D
Non-Volatile SRAM MODULE 2Mbit (128K x 16-Bit), 40pin-Dip, 5V
Part No. HMN12816D
GENERAL DESCRIPTION
The HMN12816D 128K x 16 nonvolatile SRAM’s are 2,097,152-bit fully static, nonvolatile SRAM’s, organized as
131,072 words by 16 bits. Each NVSRAM has a self contained lithium energy source and control circuitry which
constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is
automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package
HMN12816D devices can be used in place of solutions which build nonvolatile 128Kx16 memory by utilizing a
variety of discrete components. There is no limit on the number of write cycles that can be executed and no additional
support circuitry is required for microprocessor interfacing.
The HMN12816D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w
Access time : 70, 85, 120, 150ns
w
High-density design : 256KByte Design
w
Battery internally isolated until power is applied
w
Industry-standard 40-pin 128K x 16 pinout
w
Unlimited write cycles
w
Data retention in the absence of V
CC
w
10-years minimum data retention in absence of power
w
Automatic write-protection during power-up/power-down
cycles
w
Data is automatically protected during power loss
w
Conventional SRAM operation; unlimited write cycles
PIN ASSIGNMENT
/CEU
/CEL
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Vss
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
/WE
A16
A15
A14
A13
A12
A11
A10
A9
Vss
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPTIONS
w
Timing
70 ns
85 ns
120 ns
150 ns
MARKING
- 70
- 85
-120
-150
40-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
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HANBit Electronics Co.,Ltd
HANBit
HMN12816D
FUNCTIONAL DESCRIPTION
The HMN12816D devices execute a read cycle whenever /WE (Write Enable) is inactive (high) and either/both of /CEU or
/CEL (Chip Enables) are active (low) and /OE (Output Enable) is active (low). The unique address specified by the 17
address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of /CEU and /CEL
determines whether all or part of the addressed word is accessed. If /CEU is active with /CEL inactive, then only the upper
byte of the addressed word is accessed. If /CEU is inactive with /CEL active, then only the lower byte of the addressed
word is accessed. If both the /CEU and /CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will
be available to the 16 data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that /CEU, /CEL and /OE access times are also satisfied. If /CEU, /CEL, and /OE access times are not satisfied, then data
access must be measured from the later occurring signal, and the limiting parameter is either t
CO
for /CEU, /CEL, or t
OE
for
/OE rather than address access.
The HMN12816D devices execute a write cycle whenever /WE and either/both of /CEU or /CEL are active (low) after
address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072
words of data is accessed. The status of /CEU and /CEL determines whether all or part of the addressed word is
accessed. If /CEU is active with /CEL inactive, then only the upper byte of the addressed word is accessed. If /CEU is
inactive with /CEL active, then only the lower byte of the addressed word is accessed. If both the /CEU and /CEL inputs
are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of /CEU
and/or /CEL, or WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for
a minimum recovery time (t
WR
) before another cycle can be initiated. The /OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (/CEU and/or /CEL, and /OE active)
then /WE will disable the outputs in t
ODW
from its falling edge.
PIN DESCRIPTION
A
0
-A
16
: Address Inputs
/CEU : Chip enable upper byte
/CEL : Chip enable lower byte
DQ
0
-DQ
15
: Data input / Data output
/WE : Write enable
/OE : Output enable
V
CC
: +5V power supply
V
ss
: Ground
/CEL
/CEU
/OE
/WE
BLOCK DIAGRAM
2 x 128K x 8
SRAM
Block
Power
/CEL
A
0
-A
16
DQ
0
-DQ15
/CEU
Power
–
Fail
Control
Lithium
Cell
V
CC
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Rev. 0.0 (April, 2002)
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HANBit Electronics Co.,Ltd
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HMN12816D
READ/WRITE FUNCTION
CYCLE
PERFORMED
Output Disabled
/OE
H
L
L
L
X
X
X
X
/WE
H
H
H
H
L
L
L
X
/CEL
X
L
L
H
L
L
H
H
/CEU
X
L
H
L
L
H
L
H
VCC CURRENT
I
CCO
I
CCO
DQ0-DQ7
High-Z
Output
Output
High-Z
Input
DQ8-DQ15
High-Z
Output
High-Z
Output
Input
High-Z
Input
High-Z
Read Cycle
I
CCO
I
CCS
Input
High-Z
High-Z
Write Cycle
Output Disabled
DATA RETENTION MODE
The HMN12816D provides full functional capability for V
CC
greater than 4.5 volts and write protects by 4.25volts. Data is
maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile static RAMs constantly monitor
V
CC
. Should the supply volt-age decay, the NV SRAM’s automatically write protect themselves, all inputs become "don't
care," and all out-puts become high impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit
connects the lithium energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC voltage applied on V
CC
relative to V
SS
DC Voltage applied on any pin excluding V
CC
relative to V
SS
Operating temperature
Storage temperature
Temperature under bias
Soldering temperature
SYMBOL
V
CC
V
T
T
OPR
T
STG
T
BIAS
T
SOLDER
RATING
-0.3V to 7.0V
-0.3V to 7.0V
0 to 70°C
-40°C to 70°C
-10°C to 70°C
260°C
For 10 second
Functional operation
should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
V
T
≤
V
CC
+0.3
CONDITIONS
NOTE:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
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Rev. 0.0 (April, 2002)
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HANBit Electronics Co.,Ltd
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RECOMMENDED DC OPERATING CONDITIONS
( T
A
= T
OPR
)
PARAMETER
Supply Voltage
Ground
Input high voltage
Input low voltage
SYMBOL
V
CC
V
SS
V
IH
V
IL
MIN
4.5V
0
2.2
-0.3
TYPICAL
5.0V
0
-
-
HMN12816D
MAX
5.5V
0
Vcc+0.3V
0.8V
NOTE:
Typical values indicate operation at T
A
= 25℃
DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
O
C to 70
O
C )
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
³V
IH
£V
CC
Output Current @ 2.4V
Output Current @0.4V
Standby Current
/CEU,/CEL=2.2V
Standby Current
/CEU,/CEL=Vcc-0.5V
Operating Current
I
CCS2
I
CCO1
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
MIN
-2.0
-1.0
-1.0
2.0
-
TYP.
-
-
-
-
10
MAX
+2.0
+1.0
-
-
20
UNIT
mA
mA
mA
mA
mA
-
-
6
10
170
mA
mA
CAPACITANCE
(T
A
=25℃ , f=1MHz, V
CC
=5.0V)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
20
5
MAX
25
10
UNITS
pF
pF
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Rev. 0.0 (April, 2002)
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READ CYCLE
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Read Cycle Time
Address Access Time
Chip enable access time
Output enable to Output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output high Z
Output hold from address change
SYMBOL
t
RC
t
ACC
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
CONDITIONS
-70
MIN
70
-
-
-
5
5
0
0
10
MAX
-
70
70
35
-
-
25
25
-
MIN
85
-
-
-
5
0
0
0
10
-85
MAX
-
85
85
45
-
-
35
25
-
-120
MIN
120
-
-
-
5
0
0
0
10
HMN12816D
-150
MIN
150
-
-
-
10
5
0
0
10
MAX
-
150
150
70
-
-
60
50
-
MAX
-
120
120
60
-
-
45
35
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(T
A
= T
OPR
, V
ccmin
£
V
cc
≤
V
ccmax
)
PARAMETER
Write Cycle Time
Chip enable to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
SYMBOL
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
DW
t
DH1
t
DH2
t
WZ
t
OW
Note 4
Note 4
Note 5
Note 5
Note 1
Note 2
Note 1
Note 1
Note 3
Note 3
CONDITIONS
-70
MIN
70
65
0
65
55
5
15
30
0
10
0
5
MAX
-
-
-
-
-
-
-
-
-
-
25
-
MIN
85
75
0
75
65
5
15
35
0
10
0
0
-85
MAX
-
-
-
-
-
-
-
-
-
-
30
-
-120
MIN
120
100
0
100
85
5
15
45
0
10
0
0
MAX
-
-
-
-
-
-
-
-
-
-
40
-
-150
Min
150
100
0
90
90
5
15
50
0
0
0
5
Max
-
-
-
-
-
-
-
-
-
-
50
-
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either t
WR1
or t
WR2
must be met.
4. Either t
DH1
or t
DH2
must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
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Rev. 0.0 (April, 2002)
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