®
HI5860
Data Sheet
February 6, 2008
FN4654.7
12-Bit, 130MSPS, High Speed D/A
Converter
The HI5860 is a 12-bit, 130MSPS (Mega Samples Per
Second), high speed, low power, D/A converter which is
implemented in an advanced CMOS process. Operating
from a single +3V to +5V supply, the converter provides
20mA of full scale output current and includes
edge-triggered CMOS input data latches. Low glitch energy
and excellent frequency domain performance are achieved
using a segmented current source architecture.
This device complements the HI5x60 and HI5x28 family of high
speed converters, which includes 8-, 10-, 12-, and 14-bit
devices.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 130MSPS
• Low Power . . . 175mW at 5V, 32mW at 3V (At 100MSPS)
• Integral Linearity Error (Typ) . . . . . . . . . . . . . . . ±0.5 LSB
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• Power-Down Mode
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(76dBc, f
S
= 50MSPS, f
OUT
= 2.51MHz)
• Excellent Multitone Intermodulation Distortion
• Pb-Free Available (RoHS Compliant)
Pinout
HI5860
(28 LD SOIC, TSSOP)
TOP VIEW
(MSB) D11
1
28 CLK
27 DV
DD
26 DCOM
25 ACOM
24 AV
DD
23 COMP2
22 IOUTA
21 IOUTB
20 ACOM
19 COMP1
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
Applications
• Basestations (Cellular, WLL)
• Medical/Test Instrumentation
• Wireless Communications Systems
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
D10 2
D9 3
D8 4
D7 5
D6 6
D5 7
D4 8
D3 9
D2 10
D1 11
(LSB) D0 12
NC 13
NC 14
Ordering Information
PART
NUMBER
HI5860IA*
HI5860IB
HI5860IBZ*
(Note)
HI5860SOICEVAL1
PART MARKING
HI5860 IA
HI5860IB
HI5860IBZ
TEMP. RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
+25
PACKAGE
28 Ld TSSOP
28 Ld SOIC
28 Ld SOIC (Pb-free)
Evaluation Platform
PKG. DWG. #
M28.173
M28.3
M28.3
CLOCK SPEED
130MHz
130MHz
130MHz
130MHz
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5860
Typical Applications Circuit
HI5860
NC (13, 14)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11 (1)
D10 (2)
D9 (3)
D8 (4)
D7 (5)
D6 (6)
D5 (7)
D4 (8)
D3 (9)
D2 (10)
D1 (11)
D0 (LSB) (12)
CLK (28)
(21) IOUTB
(23) COMP2
(19) COMP1
DCOM (26)
BEAD
+
10µF
10µH
0.1µF
DV
DD
(27)
(24) AV
DD
0.1µF
(20) ACOM
0.1µF
0.1µF
FERRITE
BEAD
10µH
+
10µF
+5V OR +3V (V
DD
)
50Ω
D/A OUT
(22) IOUTA
50Ω
(18) FSADJ
R
SET
D/A OUT
1.91kΩ
(25) ACOM
(15) SLEEP
(16) REFLO
(17) REFIO
0.1µF
ACOM
DCOM
50Ω
Functional Block Diagram
IOUTA
IOUTB
(LSB) D0
D1
D2
D3
D4
D5
LATCH
D6
D7
D8
D9
D10
(MSB) D11
COMP2
COMP1
CLK
INT/EXT
SELECT
REFERENCE
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
UPPER
5-BIT
DECODER
31
LATCH
38
SWITCH
MATRIX
38
7 LSBs
+
31 MSB
SEGMENTS
CASCODE
CURRENT
SOURCE
AV
DD
ACOM
DV
DD
DCOM
REFLO
REFIO
FSADJ SLEEP
2
FN4654.7
February 6, 2008
HI5860
Pin Descriptions
PIN NUMBER
1 through 12
PIN NAME
D11 (MSB) Through
D0 (LSB)
NC
SLEEP
PIN DESCRIPTION
Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
13,14
15
No Connect. (Available as 2 additional LSBs on the HI5960, 14-bit device).
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20μA active pull-down current.
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal
reference.
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
FSADJ
/R
SET
.
For use in reducing bandwidth/noise. Recommended: Connect 0.1µF to AV
DD
.
The complementary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
Connect 0.1µF capacitor to ACOM.
Analog Supply (+2.7V to +5.5V).
Connect to Analog Ground.
Connect to Digital Ground.
Digital Supply (+2.7V to +5.5V).
Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is
latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes
through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC
being updated on the rising clock edge. For optimum spectral performance, it is recommended that the
clock edge be skewed such that set-up time is larger than the hold time.
16
REFLO
17
REFIO
18
FSADJ
19
21
COMP1
IOUTB
22
23
24
20, 25
26
27
28
IOUTA
COMP2
AV
DD
ACOM
DCOM
DV
DD
CLK
3
FN4654.7
February 6, 2008
HI5860
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV
DD
to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D11-D0, CLK, SLEEP) . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= DV
DD
= +5V (except where otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA,
T
A
= -40°C to +85°C, T
A
= +25°C for All Typical Values.
TEST CONDITIONS
MIN
(Note10)
TYP
MAX
(Note 10)
UNITS
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
12
“Best Fit” Straight Line (Note 8)
(Note 8)
(Note 8)
(Note 8)
-2.0
-1.0
-0.025
-
-
±0.5
±0.5
-
0.1
-
+2.0
+1.0
+0.025
-
Bits
LSB
LSB
% FSR
ppm
FSR/°C
% FSR
% FSR
ppm
FSR/°C
ppm
FSR/°C
mA
V
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
With Internal Reference (Notes 2, 8)
-10
-10
-
±2
±1
±50
+10
+10
-
Full Scale Gain Drift
With External Reference (Note 8)
With Internal Reference (Note 8)
-
±100
-
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Output Settling Time, (t
SETT
)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
(Note 3)
±0.05% (±2 LSB) (Note 8)
R
L
= 25Ω (Note 8)
Full Scale Step
Full Scale Step
(Notes 3, 8)
2
-0.3
-
-
20
1.25
130
-
-
-
-
-
-
-
-
35
5
2.5
2.5
10
50
30
-
-
-
-
-
-
-
-
MHz
ns
pV•s
ns
ns
pF
pA/
√Hz
pA/
√Hz
4
FN4654.7
February 6, 2008
HI5860
Electrical Specifications
AV
DD
= DV
DD
= +5V (except where otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA,
T
A
= -40°C to +85°C, T
A
= +25°C for All Typical Values.
(Continued)
TEST CONDITIONS
MIN
(Note10)
TYP
MAX
(Note 10)
UNITS
PARAMETER
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 10MHz Span (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 4MHz Span (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 8)
-
-
-
-
-
-
-
-
68
66
-
-
68
66
-
-
68
66
-
-
-
-
77
95
95
-71
-75
-76
55
66
74
-
54
62
74
-
75
64
74
-
76
78
78
76
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
+5V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 4.0MHz (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 2.0MHz (Notes 4, 8)
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
+5V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
f
CLK
= 130MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
f
CLK
= 130MSPS, f
OUT
= 10.1MHz (Notes 4, 8)
f
CLK
= 130MSPS, f
OUT
= 5.02MHz, T = +25°C (Notes 4, 8)
f
CLK
= 130MSPS, f
OUT
= 5.02MHz, T = Min to Max (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, T = +25°C (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, T = Min to Max (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = +25°C (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = Min to Max (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 8)
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
+5V Power Supply
Multitone Power Ratio
f
CLK
= 20MSPS, f
OUT
= 2.0MHz to 2.99MHz, 8 Tones at
110kHz Spacing (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 10MHz to 14.95MHz, 8 Tones at
530kHz Spacing (Notes 4, 8)
-
76
-
dBc
+3V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 8)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 8MHz Span (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 8MHz Span (Notes 4, 8)
-
-
-
-
-
-
73
92
92
-71
-75
-75
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
+3V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 4.0MHz (Notes 4, 8)
f
CLK
= 50MSPS, f
OUT
= 2.0MHz (Notes 4, 8)
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
5
FN4654.7
February 6, 2008
NXP MCU
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