IC41C16256
IC41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 512 cycles /8 ms
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR),
Hidden
• Single power supply:
5V ± 10% (IC41C16256)
3.3V ± 10% (IC41LV16256)
• Byte Write and Byte Read operation via two
CAS
• Industrail Temperature Range -40
o
C to 85
o
C
•
Pb-free package is available
•
•
•
•
DESCRIPTION
The
ICSI
IC41C16256 and IC41LV16256 is a 262,144 x 16-
bit high-performance CMOS Dynamic Random Access Memo-
ries. The IC41C16256 offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as short
as 10 ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes the IC41C16256 ideal for use in
16-, 32-bit wide data bus systems.
These features make the IC41C16256and IC41LV16256 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IC41C16256 is packaged in a 40-pin 400mil SOJ and
400mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-25(5V)
25
8
12
10
45
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATIONS
40-Pin TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
IC41C16256
IC41LV16256
Functional Description
The IC41C16256 and IC41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered 9 bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS)
.
The IC41C16256 and IC41LV16256 has two
CAS
controls,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs internally
generates a
CAS
signal functioning in an identical man-
ner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IC41C16256 and IC41LV16256
CAS
function is
determined by the first
CAS
(LCAS or
UCAS)
transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IC41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the
addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs first.
Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
5
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