Military & Space Products
32K x 8 STATIC RAM
FEATURES
RADIATION
• Fabricated with RICMOS
™
IV Bulk
0.8
µm
Process (L
eff
= 0.65
µm)
• Total Dose Hardness through 1x10
6
rad(SiO
2
)
• Neutron Hardness through 1x10
14
cm
-2
• Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
• Soft Error Rate of <1x10
-10
upsets/bit-day
• Dose Rate Survivability through 1x10
12
rad(Si)/s
• Latchup Free
OTHER
HC6856
• Listed on SMD #5962-92153. Available as
MIL-PRF-38535 QML Class Q and Class V
• Read/Write Cycle Times
≤
30 ns (Typical)
≤
40 ns (-55 to 125°C)
• Standby Current of 20
µA
(typical)
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V
±
10% Power Supply
• Packaging Options
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- 28-Lead Flat Pack (0.530 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 x 8-bit static random access memory
with industry-standard functionality. It is fabricated with
Honeywell’s radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V
±
10% power supply.
The RAM is available with either TTL or CMOS compatible
I/O. Power consumption is typically less than 50 mW/MHz
in operation, and less than 5 mW/MHz in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 20 ns.
Honeywell’s enhanced RICMOS
™
IV (Radiation Insensitive
CMOS) technology is radiation hardened through the use of
advanced and proprietary design, layout, and process hard-
ening techniques. The RICMOS
™
IV process is a 5-volt,
twin-well CMOS technology with a 170 Å gate oxide and a
minimum drawn feature size of 0.8
µm
(0.65
µm
effective
gate length—L
eff
). Additional features include a three layer
interconnect metalization and a lightly doped drain (LDD)
structure for improved short channel reliability. High resis-
tivity cross-coupled polysilicon resistors have been incorpo-
rated for single event upset hardening.
HC6856
FUNCTIONAL DIAGRAM
A:0-8,12-13
Row
Decoder
•
•
•
11
32,768 x 8
Memory
Array
•
•
•
CE
NCS
NWE
Column Decoder
Data Input/Output
WE • CS • CE
8
8
DQ:0-7
NOE
CS • CE
NWE • CS • CE • OE
(0 = high Z)
Signal
1 = enabled
#
Signal
A:9-11,14
4
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
NCS
Address input pins (A) which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces
the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all
the input buffers. If this signal is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level it allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers.
If this signal is not used it must be connected to VDD.
NWE
NOE
CE
TRUTH TABLE
NCS
L
L
H
X
CE
H
H
X
L
NWE
H
L
XX
XX
NOE
L
X
XX
XX
MODE
Read
Write
Deselected
Disabled
DQ
Data Out
Data In
High Z
High Z
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
2
HC6856
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The RAM will meet all stated functional and electrical speci-
fications over the entire operating temperature range after
the specified total ionizing radiation dose. All electrical and
timing performance parameters will remain within specifica-
tions after rebound at VDD = 5.5 V and T =125°C extrapo-
lated to ten years of operation. Total dose hardness is
assured by wafer level testing of process monitor transistors
and RAM product using 10 keV X-ray radiation. Transistor
gate threshold shift correlations have been made between
10 keV X-rays applied at a dose rate of 1x10
5
rad(SiO
2
)/min
at T = 25°C and gamma rays (Cobalt 60 source) to ensure
that wafer level X-ray testing is consistent with standard
military radiation test environments.
The RAM will meet any functional or electrical specification
after exposure to a radiation pulse of
≤
50 ns duration up to
1x10
12
rad(Si)/s, when applied under recommended oper-
ating conditions. Note that the current conducted during the
pulse by the RAM inputs, outputs, and power supply may
significantly exceed the normal operating levels. The appli-
cation design must accommodate these effects.
Neutron Radiation
The RAM will meet any functional or timing specification
after a total neutron fluence of up to 1x10
14
cm
-2
applied
under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
The RAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient ionizing
radiation pulse of
≤1 µs
duration up to 1x10
9
rad(Si)/s, when
applied under recommended operating conditions. To en-
sure validity of all specified performance parameters be-
fore, during, and after radiation (timing degradation during
transient pulse radiation is
≤10%),
it is suggested that a
minimum of 0.8
µF
per part of stiffening capacitance be
placed between the package (chip) VDD and VSS, with a
maximum inductance between the package (chip) and
stiffening capacitance of 0.7 nH per part. If there are no
operate-through or valid stored data requirements, the
capacitance specification can be reduced to a minimum of
0.1
µF
per part.
Soft Error Rate
The RAM is capable of soft error rate (SER) performance
of <1x10
-10
upsets/bit-day, under recommended operating
conditions. This hardness level is defined by the Adams
10% worst case cosmic ray environment.
Latchup
The RAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the RICMOS
™
p-epi
on p+ substrate process and use of proven design tech-
niques, such as double guardbanding, ensure latchup
immunity.
RADIATION HARDNESS RATINGS (1)
Limits (2)
≥1x10
6
≥1x10
9
≥1x10
12
<1x10
-9
(4)
<1x10
-10
≥1x10
14
N/cm
2
1 MeV equivalent energy,
Unbiased, TA=25°C
Parameter
Total Dose
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability
Soft Error Rate:
Level A
Level Z
Neutron Fluence
(1)
(2)
(3)
(4)
Units
rad(SiO
2
)
rad(Si)/s
rad(Si)/s
upsets/bit-day
Test Conditions
TA=25°C
Pulse width≤1
µs
Pulse width≤50 ns, X-ray,
VDD=6.6 V, TA=25°C
Adams 10%
worst case environment
Device will not latch up due to any of the specified radiation exposure conditions.
Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
Suggested stiffening capacitance specifications for optimum expected dose rate upset performance is stated above in the text.
SER <1x10
-10
u/b-d from -55 to 80°C.
3
HC6856
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
Parameter
Positive Supply Voltage (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature • Time
Total Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
28 FP/36 FP
28 DIP
TJ
Junction Temperature
2000
2
10
175
Min
-0.5
-0.5
-65
Max
7.0
VDD+0.5
150
270•5
2.5
25
Units
V
V
°C
°C•s
W
mA
V
°C/W
°C/W
°C
Θ
JC
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
4.5
-55
-0.3
Typ
5.0
25
Max
5.5
125
VDD+0.3
Units
V
°C
V
CAPACITANCE (1)
Worst Case
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
4
6.5
Max
6
8
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter (2)
Data Retention Voltage
(3)
Data Retention Current
Typical
(1)
2.0
150
Worst Case
Min
2.5
400
Max
V
µA
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Units
Test Conditions
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
4
HC6856
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB1
IDDSB2
IDDOPW
IDDOPR
II
IOZ
VIL
Parameter
Static Supply Current
Static Supply Current with Chip Disabled
Dynamic Supply Current, Selected
(Write)
Dynamic Supply Current, Selected
(Read)
Input Leakage Current
Output Leakage Current
Low-Level InputVoltage
CMOS
TTL
CMOS
TTL
Typical Worst Case
(2)
Units
(1)
Min
Max
0.02
0.02
5.5
4.5
±0.05
±0.1
1.9
1.3
3.0
1.7
0.2
0.7xVDD
Test Conditions
(3)
VIH=VDD IO=0
VIL=VSS Inputs Stable
CE=VSS or NCS=VDD
IO=0, VSS≤ VI≤VDD (4)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
VSS≤VI≤VDD
VSS≤VIO≤VDD
Output=high Z
VDD=4.5V
VDD=4.5V
VDD=5.5V
VDD=5.5V
VDD=4.5V, IOL=10 mA
VDD=4.5V, IOL=200
µA
VDD=4.5V, IOH=-5 mA
VDD=4.5V, IOH=-200
µA
1.2
1.2
7.5
6.5
-5
-10
+5
10
0.3xVDD
mA
mA
mA
mA
µA
µA
V
V
V
V
0.8
VIH
High-Level Input Voltage
2.2
0.4
0.05
4.2
V
DD
-0.05
VOL
Low-Level Output Voltage
V
V
V
V
4.8
VOH
(1)
(2)
(3)
(4)
(5)
High-Level Output Voltage
Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
Input high = VIH
≥
VDD-0.3V, input low =VIL
≤
0.3V
Guaranteed but not tested.
All inputs switching. DC average current.
2.9 V
Vref1
249Ω
DUT
output
Vref2
+
-
Valid high
output
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
Real-time operating system RTOS
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