PRELIMINARY DATA SHEET
128MB DDR SDRAM S.O. DIMM
HB54A1288KM
(16M words
×
64 bits, 1 Bank)
Description
The HB54A1288KM is a 16M
×
64
×
1 bank Double
Data Rate (DDR) SDRAM Module, mounted 4 pieces
of 256Mbits DDR SDRAM (HM5425161BTT) sealed in
TSOP package and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture.
Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 200-pin socket type package (dual lead
out).
Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
•
200-pin socket type package (dual lead out)
Outline: 67.6mm (Length)
×
31.75mm (Height)
×
3.80mm (Thickness)
Lead pitch: 0.6mm
•
2.5V power supply (VCC/VCCQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 133MHz/100MHz (max.)
•
Data inputs and outputs are synchronized with DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 2, 2.5
•
8192 refresh cycles: 7.8µs (8192/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0190H10 (Ver. 1.0)
Date Published September 2001 (K)
Printed in Japan
URL: http://www.elpida.com
C
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Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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Elpida Memory, Inc. 2001
t
HB54A1288KM
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/S0
CKE0
Function
Address input
Row address
Column address
A0 to A12
A0 to A8
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VCC indentication flag
EO
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7
SCL
SDA
SA0 to SA2
VCC
VCCSPD
VREF
VSS
VCCID
NC
Preliminary Data Sheet E0190H10 (Ver. 1.0)
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No connection
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4
HB54A1288KM
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Bit1 Bit0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
Hex value
80
08
07
0D
09
01
40
00
04
70
75
80
70
80
00
82
10
00
01
0E
04
Comments
128
256 byte
SDRAM DDR
13
9
1
64 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
EO
-B75B
-10B
10
-10B
11
12
13
14
15
16
17
18
19
20
21
22
23
-B75B/10B
24
-10B
25
26
27
Voltage interface level of this assembly 0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
DDR SDRAM cycle time, CL = X
-A75B
SDRAM access from clock (tAC)
-A75B/B75B
0.7ns*
5
0.8ns*
5
Non-parity
7.8 µs
Self refresh
×
16
Not used
1 CLK
2, 4, 8
4
2/2.5
0
1
Unbuffered
± 0.2V
CL = 2*
5
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 1
-A75B
Maximum data access time (tAC) from
0
clock at CLX - 1
-A75B/B75B
1
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Minimum row precharge time (tRP)
0
Preliminary Data Sheet E0190H10 (Ver. 1.0)
L
od
Pr
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0C
01
02
20
00
75
uc
A0
70
0.7ns*
5
0.8ns*
5
80
00
00
50
t
20ns
5
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