HB52R649E1U-A6B/B6B
512 MB Registered SDRAM DIMM
64-Mword
×
72-bit, 100 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M
×
4 Components)
PC100 SDRAM
EO
Description
Features
E0022H10 (1st edition)
(Previous ADE-203-1192A (Z))
Preliminary
Jan. 31, 2001
The HB52R649E1U belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed
as an optimized main memory solution for 8-byte processor applications. The HB52R649E1U is a 64M
×
72
×
1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM
(HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece
of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R649E1U is 168-pin socket
type package (dual lead out). Therefore, the HB52R649E1U makes high density mounting possible without
surface mount technology. The HB52R649E1U provides common data inputs and outputs. Decoupling
capacitors are mounted beside each TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
•
Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev.1.2)
•
168-pin socket type package (dual lead out)
Outline: 133.35 mm (Length)
×
30.48 mm (Height)
×
4.80 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
Preliminary: The Specifications of this device are subject to change without notice. Please contact to your
nearest Elpida Memory, Inc. regarding specifications.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
Pr
od
t
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HB52R649E1U-A6B/B6B
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8
•
2 variations of burst sequence
Sequential
Interleave
•
Programmable
CE
latency
: 3/4 (HB52R649E1U-A6B)
: 4 (HB52R649E1U-B6B)
EO
•
2 variations of refresh
Auto refresh
Self refresh
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64 ms
Ordering Information
Type No.
HB52R649E1U-A6B
HB52R649E1U-B6B
Pin Arrangement
L
Frequency
100 MHz
100 MHz
4
CE
latency
3/4
Package
Contact pad
168-pin dual lead out socket type Gold
1 pin 10 pin 11 pin
85 pin 94 pin 95 pin 124 pin 125 pin
Preliminary Data Sheet E0022H10
2
Pr
40 pin 41 pin
84 pin
od
168 pin
t
uc
HB52R649E1U-A6B/B6B
Pin No.
1
2
3
4
5
6
7
8
9
Pin name
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
Pin No.
43
44
45
46
47
Pin name
V
SS
NC
S2
DQMB2
DQMB3
NC
V
CC
NC
NC
CB2
CB3
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin name
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Pin name
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
EO
48
DQ4
DQ5
DQ6
49
50
51
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQ7
DQ8
V
SS
DQ9
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
CC
W
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
L
V
SS
V
CC
NC
NC
NC
V
SS
V
SS
V
CC
DQ16
DQ17
DQ18
DQ19
Preliminary Data Sheet E0022H10
3
Pr
101
DQ20
102
V
CC
103
104
105
CB4
106
CB5
V
SS
DQ21
DQ22
DQ23
107
108
109
110
NC
NC
V
CC
DQ24
DQ25
DQ26
DQ27
111
CE
112
113
114
115
116
117
118
119
NC
RE
V
SS
A1
A3
A5
DQ28
DQ29
DQ30
DQ31
DQ45
DQ46
DQ47
od
149
150
151
152
153
DQMB4
DQMB5
154
155
156
157
158
159
160
161
t
uc
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
HB52R649E1U-A6B/B6B
Pin No.
36
37
38
39
40
41
42
Pin name
A6
A8
A10 (AP)
BA1
V
CC
V
CC
Pin No.
78
79
80
Pin name
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin No.
120
121
122
123
124
125
126
Pin name
A7
A9
BA0
A11
V
CC
CK1
A12
Pin No.
162
163
164
165
166
167
168
Pin name
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
EO
81
82
83
CK0
84
Pin Description
Pin name
A0 to A12
L
Function
Address input
Row address A0 to A12
Column address A0 to A9, A11
Bank select address
Data input/output
BA0/BA1
DQ0 to DQ63
CB0 to CB7
S0, S2
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
REGE*
1
SDA
SCL
SA0 to SA2
V
CC
V
SS
NC
Note:
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
Preliminary Data Sheet E0022H10
4
Pr
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Write protect for serial PD
Register enable
Clock input for serial PD
Serial address input
Ground
No connection
Check bit (Data input/output)
Data input/output for serial PD
Primary positive power supply
od
t
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HB52R649E1U-A6B/B6B
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
80
08
04
0D
0B
01
48
00
01
A0
128
256 byte
SDRAM
13
11
1
72 bit
0 (+)
LVTTL
CL = 3
EO
Number of banks
Module data width
SDRAM cycle time
(highest
CE
latency)
10 ns
10
11
12
Refresh rate/type
13
14
15
SDRAM width
16
17
18
(-B6B)
19
20
21
Number of row addresses bits
Number of column addresses
bits
Module data width (continued)
Module interface signal levels
SDRAM access from Clock
(highest
CE
latency)
6 ns
Module configuration type
Error checking SDRAM width
SDRAM device attributes:
0
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
(-A6B)
0
0
SDRAM device attributes:
S
latency
SDRAM device attributes:
W
latency
SDRAM device attributes
L
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
60
*
7
Preliminary Data Sheet E0022H10
5
Pr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
0
02
82
ECC
Normal
(7.8125 µs)
Self refresh
64M
×
4
×
4
1 CLK
0
0
0
0
0
1
04
04
01
od
1
0
1
0
0F
04
1
0
06
0
0
0
1
0
04
1
1
0
01
01
16
1, 2, 4, 8
4
t
uc
2/3
3
0
0
Registered