5962R0623801VXC datasheet, PDF

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5962R0623801VXC: DescriptionParallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20; Categorylogic logic; File Size366KB，28 Pages; ManufacturerCobham PLC

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5962R0623801VXC Overview

Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20

5962R0623801VXC Parametric

Parameter Name	Attribute value
package instruction	DFP, FL20,.3
Reach Compliance Code	unknown
Counting direction	BIDIRECTIONAL
series	AC
JESD-30 code	R-XDFP-F20
length	13.081 mm
Logic integrated circuit type	PARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Sup	90000000 Hz
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	DFP
Encapsulate equivalent code	FL20,.3
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	3.3/5 V
propagation delay (tpd)	14 ns
Certification status	Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	3.0988 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
Trigger type	NEGATIVE EDGE
width	7.5 mm
minfmax	80 MHz
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Technical change for I

DDQ

test in table IA. – LTG

Add die requirements with appendix A. Update boilerplate paragraphs as

specified in the current MIL-PRF-38535 requirements. – MAA

Add subgroups to table IIA in groups C and D. - LTG

Add equivalent test circuits and footnote 2 to figure 5. Delete class M

requirements per updated boilerplate paragraphs. - MAA

DATE (YR-MO-DA)

07-04-17

09-02-11

11-06-23

12-11-08

APPROVED

Thomas M. Hess

Charles F. Saffle

David J. Corbett

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Larry T. Gauder

CHECKED BY

Charles F. Saffle

APPROVED BY

Thomas M. Hess

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

06-12-21

REVISION LEVEL

STANDARD

MICROCIRCUIT

DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil

MICROCIRCUIT, DIGITAL, RADIATION

HARDENED, ADVANCED CMOS, 8-BIT

UNIVERSAL SHIFT/STORAGE REGISTER WITH

THREE-STATE OUTPUTS, MONOLITHIC SILICON

SIZE

CAGE CODE

AMSC N/A

DSCC FORM 2233

APR 97

67268

SHEET

5962-06238

1 OF 27

5962-E037-13

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein.

3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V.

3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Function table. The function table shall be as specified on figure 3.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4.

3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.

3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document

revision level control and shall be made available to the preparing and acquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table IA.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance

submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the

manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein .

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall

be provided with each lot of microcircuits delivered to this drawing.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-06238

SHEET

5962R0623801VXC Related Products

	5962R0623801VXC	5962R0623801QXA	5962R0623801VXA	5962R0623801QXC	5962R0623801Q9A
Description	Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20	Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20	Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20	Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DFP-20	Parallel In Parallel Out, AC Series, 8-Bit, Bidirectional, True Output, CMOS, DIE-64
package instruction	DFP, FL20,.3	DFP, FL20,.3	DFP, FL20,.3	DFP, FL20,.3	DIE-64
Reach Compliance Code	unknown	unknown	unknown	unknown	unknow
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	AC	AC	AC	AC	AC
JESD-30 code	R-XDFP-F20	R-XDFP-F20	R-XDFP-F20	R-XDFP-F20	R-XUUC-N64
Logic integrated circuit type	PARALLEL IN PARALLEL OUT	PARALLEL IN PARALLEL OUT	PARALLEL IN PARALLEL OUT	PARALLEL IN PARALLEL OUT	PARALLEL IN PARALLEL OUT
Number of digits	8	8	8	8	8
Number of functions	1	1	1	1	1
Number of terminals	20	20	20	20	64
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DFP	DFP	DFP	DFP	DIE
Encapsulate equivalent code	FL20,.3	FL20,.3	FL20,.3	FL20,.3	DIE OR CHIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	UNCASED CHIP
power supply	3.3/5 V	3.3/5 V	3.3/5 V	3.3/5 V	3.3/5 V
propagation delay (tpd)	14 ns	14 ns	14 ns	14 ns	14 ns
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	FLAT	FLAT	FLAT	FLAT	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL	UPPER
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	POSITIVE EDGE
length	13.081 mm	13.081 mm	13.081 mm	13.081 mm	-
Maximum Frequency@Nom-Sup	90000000 Hz	90000000 Hz	90000000 Hz	90000000 Hz	-
Maximum seat height	3.0988 mm	3.0988 mm	3.0988 mm	3.0988 mm	-
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	-
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm	-
Base Number Matches	1	1	1	1	-

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