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5962H9655901VEA

Description
Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDIP16, CERAMIC, DIP-16
Categorylogic    logic   
File Size243KB,19 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962H9655901VEA Overview

Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDIP16, CERAMIC, DIP-16

5962H9655901VEA Parametric

Parameter NameAttribute value
package instructionDIP, DIP16,.3
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
Counting directionRIGHT
seriesACT
JESD-30 codeR-GDIP-T16
JESD-609 codee0
Logic integrated circuit typePARALLEL IN SERIAL OUT
Maximum Frequency@Nom-Sup71000000 Hz
Number of digits8
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
propagation delay (tpd)21 ns
Certification statusQualified
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose1M Rad(Si) V
Trigger typePOSITIVE EDGE
minfmax71 MHz
Base Number Matches1
REVISIONS
LTR
A
B
DESCRIPTION
Changes in accordance with NOR 5962-R101-97 – CFS.
Incorporate Revision A. Update boilerplate to MIL-PRF-38535 requirements. –
LTG
Correct title to more accurately describe the function. Update radiation
features in section 1.5. Update the boilerplate paragraphs to current
requirements as specified in MIL-PRF-38535. - jak
To correct switching waveforms input/output test limits to figure 4. Add test
equivalent circuits and footnote 4 to figure 4. Delete class M requirements
throughout.—MAA
DATE (YR-MO-DA)
96-11-18
01-11-01
APPROVED
Monica L. Poelking
Thomas M. Hess
C
10-01-19
Thomas M. Hess
D
13-01-25
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
D
15
D
16
D
17
D
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHECKED BY
Thanh V. Nguyen
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
96-07-16
REVISION LEVEL
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, 8-BIT
SERIAL/PARALLEL-IN, SERIAL-OUT SHIFT
REGISTER, TTL COMPATIBLE INPUTS,
MONOLITHIC SILICON
SIZE
CAGE CODE
D
A
67268
SHEET 1 OF
5962-96559
18
DSCC FORM 2233
APR 97
5962-E184-13
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